Solid-State Devices TRIZ Cases

A nonvolatile memory device uses a stacked-layer structure with oxygen-deficient and oxygen-rich transition metal oxide layers to stabilize current density.

Aromatic solvent inkjet fluid deposits organic semiconductor layers with controlled evaporation rates.

Stripping the rigid substrate in a connection region eliminates visible seams between adjacent sub-screens, enhancing multi-screen display quality.

A display device lens layer uses a higher refractive index material to expand the visual field angle.

Maskless ion implantation forms buried impurity layers to boost current driving capability while eliminating mask-related fabrication complexity.

A polyhedral lighting device positions light emitting elements to surround a central region.

A sacrificial layer enables complete mirror coating of optical component lateral surfaces via sputtering or vapor deposition.

Controller overwrites NAND flash data to a higher threshold voltage level, eliminating copy operations and reducing erase verification time.

A seeding layer induces in situ crystal growth in polycrystalline silicon channels to increase grain size and electrical conductivity.

A biasing circuit applies voltage to the substrate of a phase-change memory device to reduce current flow in word lines.

Dichroic dyes absorb external light between emission peaks to improve contrast ratio without reducing luminance in display devices.

Segmented two-component resin mixing prevents uneven emission color and chromaticity variations in light emitting devices.

Selective etching of a bi-layer dielectric structure enables independent spacer thickness control for CMOS transistors.

Alternating dry etch and cleaning steps remove residues to prevent stack layer inclination during non-volatile memory trench formation.

A spontaneous polarization insulator layer enables ambipolar organic transistors to switch between p-type and n-type modes without breakdown.

A compact backlight component uses semiconductor chips on a radiation-transparent substrate to generate 360-degree light emission.

Applying a fluid, crosslinkable protective layer under vacuum conditions protects organic stacks from environmental damage while reducing process complexity.

Backside magnetic tunnel junction integration with spin orbit torque switching reduces write error rates by lowering current density requirements.

A conductive layer within OLED thin film encapsulation enables post-assembly impurity removal via voltage application.

Sacrificial oxidation offsets oxide dissolution to maintain dielectric layer thickness uniformity below 3%.

Catadioptric relay optics fold the optical path between object and image planes, reducing axial distance while correcting odd-order aberrations.

A releasing pattern exposes the pad region during lens formation, simplifying optical film removal and improving fabrication efficiency.

Laser light passes through a support substrate to activate a metal oxide release layer, generating gas pressure that detaches the resin without decomposition.

Vertical stacking of FeFET cells with metal oxide buffer layers achieves significant threshold voltage shifts for reliable data storage.

Auxiliary electrodes reduce injection barriers to balance electron and hole flow, extending device lifetime.

An organic hole transport layer reduces dark current in a quantum dot photodetector, improving infrared sensitivity for image sensors.

A 3D memory fabrication method uses sacrificial layers to enable gate replacement processes within bottom select gate cuts.

A semiconductor device uses an oxide semiconductor storage gate to store data by switching between conductive and insulative states.

Organic vapor jet printing deposits laterally patterned organic layers with varying thicknesses onto OLED substrates.

Sintering sub-micron silver particles with metal oxide at 150 to 320 degrees Celsius forms conductive material without adhesives.

Opposing touch lines equalize parasitic capacitance differences to resolve sensitivity non-uniformity in display apparatuses.

An insulating film isolates charge storage layers between adjacent vertical transistors, reducing trap levels and improving charge retention reliability.

A grid-shaped composite structure merges metal grids with deep trench isolation in backside-illuminated CMOS image sensors.

A particle-containing substrate layer scatters trapped light to improve extraction efficiency in organic electronic devices.

A thermal-sensitive layer adjusts light transmittance based on temperature changes to stabilize LED color output.

Alternating TiON layers with controlled oxygen profiles suppress stress changes and resist hydrofluoric acid in DRAM capacitors.

A wafer composite uses sacrificial material to separate an auxiliary substrate from a donor substrate for semiconductor manufacturing.

Forming the resistor element before contacts allows high-temperature annealing for near zero ppm TCR without damaging later structures.

A water-soluble mask enables precise wet etching of organic compound layers in display manufacturing.

Differential gate insulation thickness in SiC MOSFET cells suppresses stacking fault growth and reduces ON resistance without shrinking the active region area.

Laser welding secures a cover plate to a wafer along division lines, eliminating adhesive squeeze-out that damages delicate device chips during dicing.

An isolating portion in the protection layer reflects diffused light, suppressing leakage between adjacent elements while maintaining water protection.

Etching serpentine trenches in a silicon carrier wafer forms a capacitor that frees printed circuit board space for image sensor packages.

A ferroelectric memory device uses a variable thickness gate insulation layer within a trench to store multiple logic levels.

A cooler design joins press-molded plates to form tubes, eliminating extruded inner walls and reducing fabrication costs.

Two-step patterning with dielectric films controls finFET memory gate sidewalls, preventing dopant contamination in the charge trap layer.

Merged selection line layers simplify voltage control and prevent structural leaning in stacked 3D memory arrays.

Segmented nanodot growth relaxes lattice stress, eliminating phosphorescent conversion losses and enabling direct green to red LED emission.

Segmented transport layers balance electron and hole injection in a perovskite light-emitting device, resolving unipolar transport inefficiencies.

Thinned dummy dies match logic and memory stack heights, reducing thermal interface material thickness to resolve heat dissipation bottlenecks.