Vertical Transistor Charge Storage Isolation

Solution Overview

Problem

In semiconductor memory devices using vertical transistors, charge storage layers between adjacent memory cells are connected, leading to poor charge retention characteristics due to charge leakage between cells.

Innovation Solution

The charge storage layers are isolated between adjacent memory cells by forming a silicon dioxide or silicon oxynitride film, either through oxidation or selective etching, to prevent charge transfer between cells, thereby improving charge retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If charge storage layers are connected between vertically adjacent memory cells, then device complexity is reduced and manufacturing is simplified, but charge retention reliability deteriorates due to charge leakage between cells

Engineering Contradiction:

Improvestructure complexityVSAvoidcharge retention characteristic

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The charge storage layer is segmented into isolated regions between vertically adjacent memory cells using an insulating film. This segmentation prevents charge leakage between cells while maintaining the simplified vertical transistor structure, resolving the contradiction between structural simplicity and charge retention reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An insulating film is introduced as an intermediary layer between charge storage layers of vertically adjacent cells. This intermediary prevents direct charge transfer between cells while maintaining the overall structural simplicity of the vertical transistor configuration

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If charge storage layers are isolated between adjacent memory cells, then charge retention reliability is improved, but device complexity increases and manufacturing becomes more difficult

Engineering Contradiction:

Improvecharge retention characteristicVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The charge storage layer is segmented into isolated regions between vertically adjacent memory cells using an insulating film. This segmentation prevents charge leakage between cells while maintaining the simplified vertical transistor structure, resolving the contradiction between structural simplicity and charge retention reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An insulating film is introduced as an intermediary layer between charge storage layers of vertically adjacent cells. This intermediary prevents direct charge transfer between cells while maintaining the overall structural simplicity of the vertical transistor configuration

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If conventional isolation methods are used, then charge retention is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvecharge retention characteristicVSAvoidisolation precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The insulating film is formed to automatically provide isolation between charge storage layers through standard deposition processes. The film's inherent insulating properties provide the isolation function without requiring precise alignment or complex patterning steps, reducing manufacturing precision requirements while ensuring charge retention

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This isolation method enhances charge retention by reducing trap levels between cells, allowing charges to be stored reliably within individual memory cells without leaking into adjacent cells, without requiring special processes or materials.

Implementation Method 1

a first oxidization treatment is performed on the silicon layer, thereby forming a silicon dioxide film

Methodology Applied

Scientific EffectOxidation: Oxidation

Implementation Method 2

a second oxidization treatment or a nitridation treatment is performed on the silicon layer, thereby forming a silicon oxynitride film

Methodology Applied

Scientific EffectNitridation: Nitriding

Data Source

PatentUS9293563B2Semiconductor memory device and method of manufacturing the same

Publication Date: 2016.03.22 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.