CMOS Spacer Thickness Tuning via Selective Etching
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Solution Overview
Problem
Existing methods for fabricating transistors with raised source and drain regions of different types on a shared substrate lack a reliable method to independently adjust the overlap regions, affecting the I-V characteristics, output resistance, and standby power dissipation.
Innovation Solution
A method involving the formation of a bi-layer dielectric structure on a semiconductor substrate, where the first dielectric material is selectively etched over the second dielectric material to form insulating spacers of varying thicknesses for each transistor type, allowing for independent adjustment of the overlap regions and spacer thicknesses, enabling the formation of transistors with distinct source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single spacer thickness is used for both transistor types, then the fabrication process is simplified, but the overlap regions cannot be independently adjusted, affecting I-V characteristics and standby power dissipation
Solution Approach 1:
The patent divides the spacer formation process into two independent stages: first spacers are formed for the first transistor type, then second spacers are formed for the second transistor type. This segmentation allows each transistor type to have independently optimized overlap regions while maintaining a unified fabrication flow, resolving the contradiction between process simplicity and design flexibility.
Solution Approach 2:
The patent introduces a temporal dimension to the spacer formation process by forming spacers for different transistor types at different stages. First spacers are formed before the second gate electrode deposition, while second spacers are formed after, allowing independent thickness control without requiring simultaneous formation of all spacers.
2Loss of energy
If the overlap region is reduced to lower standby power dissipation, then power efficiency improves, but the distance between gate and source/drain regions increases, affecting device speed
Solution Approach 1:
The patent applies different spacer thicknesses to different transistor types and locations on the substrate. By locally optimizing the overlap region for each transistor type based on its specific performance requirements, the invention achieves reduced standby power dissipation in critical areas while maintaining appropriate device speed through tailored overlap dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the independent tuning of overlap regions between transistors, enhancing the I-V characteristics and reducing standby power dissipation by enabling precise control over the distance between the gate and source/drain regions, thereby improving the performance of transistors with different types.
Implementation Method 1
The material of said second layer is selected so that said first dielectric material of said first layer of the bi-layer can be etched selectively over the material of said second layer
Data Source
AI summary
A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.