SiC MOSFET Stacking Fault Suppression via Differential Gate Insulation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SiC-MOSFETs face increased ON resistance due to stacking faults, which are difficult to completely eliminate, and existing solutions either reduce active region area or increase chip size and cost, while also struggling with forward current flow through body diodes.
Innovation Solution
A semiconductor device using a wider bandgap material like silicon carbide with a specific MOS gate structure arrangement, where first and second MOS gate structures have differing gate insulating film thicknesses and properties, and gate electrodes connected to the source electrode, allowing reverse current to flow and reducing stacking fault growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC-MOSFET structure is used with body diodes, then current commutation is achieved, but stacking faults grow due to forward current flow through body diodes, increasing ON resistance
Solution Approach 1:
The patent divides the MOSFET structure into multiple unit cells, each containing a MOS gate and an adjacent body diode. By segmenting the device into repeating units with controlled spatial arrangement, the patent enables differential gating strategies where MOS gates can be independently controlled to prevent forward current flow through body diodes while maintaining current commutation functionality.
Solution Approach 2:
The patent introduces drift regions as intermediary elements positioned between the body diodes and current paths. These drift regions act as mediators that control current flow distribution, preventing direct forward current flow through body diodes that would cause stacking faults, while still allowing proper current commutation through the MOSFET channels.
2Object-generated harmful factors
If solutions to prevent stacking faults are implemented, then stacking fault growth is suppressed, but active region area is reduced or chip size increases
Solution Approach 1:
The patent changes the electrical parameters of the drift regions, specifically adjusting their impurity concentrations to create optimal current flow characteristics. By modifying the electrical parameters rather than physical dimensions, the patent suppresses stacking faults while maintaining full active region area utilization without increasing chip size.
3Ease of operation
If forward current is allowed through body diodes for current commutation, then inverter operation is achieved, but ON resistance increases due to stacking fault growth
Solution Approach 1:
The patent implements dynamic control of the MOS gates adjacent to body diodes during switching operations. By dynamically adjusting gate voltages based on operating conditions, the patent prevents forward current flow through body diodes during critical switching transitions, thereby suppressing stacking fault growth and reducing ON resistance while maintaining inverter operational capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device suppresses the growth of stacking faults, reduces ON resistance, and maintains a large active region area without increasing chip size, thereby improving current capability and reducing costs.
Implementation Method 1
at least one of physical properties of the respective gate electrodes, the respective gate insulating films, and the respective channel regions of first and second MOS structures is made different between the first and second MOS structures, so that a threshold voltage of each of the first MOS gate structures is different from a threshold voltage of each of the second MOS gate structures
Implementation Method 2
A semiconductor device using a wider bandgap material like silicon carbide with a specific MOS gate structure arrangement, where first and second MOS gate structures have differing gate insulating film thicknesses and properties, and gate electrodes connected to the source electrode, allowing reverse current to flow and reducing stacking fault growth
Data Source
AI summary
A semiconductor substrate made of silicon carbide is provided with first and second cells having a MOS gate structure. The first cell is a normal MOSFET cell. In the second cell, a gate electrode is directly connected to a source electrode and has a potential fixed to a potential of the source electrode. A thickness of a gate insulating film of the second cell is set to be less than a thickness of a gate insulating film of a first cell so that the surface potential of a p-type channel region of the second cell becomes lower than the surface potential of a p-type channel region of the first cell during a negative bias to the gate electrode of the first cell.