3D Ferroelectric Memory Array With Buffer Layers
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges in maintaining reliable memory storage and retrieval due to the limitations of existing memory technologies, particularly in achieving high threshold voltage shifts for accurate digital data storage in ferroelectric memory devices.
Innovation Solution
A ferroelectric memory device is developed with a 3D memory array structure, utilizing vertically stacked ferroelectric field effect transistors (FeFETs) that incorporate a ferroelectric material as a gate dielectric and an oxide semiconductor channel region, along with a buffer layer to enhance uniformity and performance, allowing for precise control of polarization and threshold voltage shifts through applied voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but memory storage reliability deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangements to a 3D vertical stack configuration, where multiple FeFET memory cells are stacked along the vertical dimension. This allows increased integration density without compromising the functional performance and storage reliability of individual cells, as each cell maintains its complete structure with proper isolation and control.
Solution Approach 2:
The patent divides the memory array into multiple independently functional FeFET cells stacked vertically, with each cell containing its own channel layer, ferroelectric layer, and electrode structures. This segmentation allows each cell to operate independently with reliable data storage while collectively achieving high integration density through vertical stacking.
2Productivity
If conventional memory structures are used in 3D configuration, then integration density increases, but threshold voltage shift control deteriorates
Solution Approach 1:
The patent introduces a buffer layer with specific material composition and controlled thickness positioned between the ferroelectric layer and dielectric layers in each FeFET cell. This local structural modification provides precise control over the electric field distribution and threshold voltage shift in each vertically stacked cell, ensuring uniform performance across all cells despite the 3D configuration.
Solution Approach 2:
The patent employs a composite structure consisting of the ferroelectric material layer combined with a buffer layer of different material properties. This composite configuration allows the buffer layer to modulate the electric field and polarization characteristics, providing precise threshold voltage control while maintaining the high integration density benefits of the vertical stack architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables improved data storage reliability and reduced error rates by achieving significant threshold voltage shifts, facilitating more efficient and accurate read/write operations in high-density memory arrays.
Implementation Method 1
The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers
Implementation Method 2
one buffer layer is disposed between the ferroelectric layer and each of the plurality of dielectric layers
Implementation Method 3
allowing for precise control of polarization and threshold voltage shifts through applied voltages
Data Source
AI summary
A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.