3D Memory Array Crystallized Channel Grain Size Control

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Solution Overview

Problem

3D memory devices face challenges in performance due to the structure of polycrystalline channel regions in memory cells, which affect electrical conductivity and efficiency, particularly in storing multiple bits per cell.

Innovation Solution

A method is developed to enhance the average grain size of polycrystalline silicon in channel regions through in situ crystal growth, using a seeding layer and annealing processes to increase conductivity, aligning the crystal structure with the substrate orientation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If polycrystalline silicon with smaller average grain size is used in channel regions, then manufacturing is easier and device density is higher, but electrical conductivity decreases and performance deteriorates

Engineering Contradiction:
Improvegrain size controlVSAvoidelectrical conductivity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by controlling the crystallization process parameters (temperature, time, seeding layer composition) to achieve optimal grain size in the polycrystalline silicon channel regions. This resolves the contradiction by finding the right parameter balance that provides both manufacturability and sufficient electrical conductivity for reliable device operation

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a seeding layer as an intermediary element that facilitates controlled crystal growth in the channel regions. This seeding layer acts as a mediator between the substrate and the polycrystalline silicon formation, enabling better grain structure control while maintaining manufacturing feasibility and improving electrical conductivity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If polycrystalline silicon with larger average grain size is used in channel regions, then electrical conductivity and performance improve, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidcrystal growth process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming a seeding layer before depositing the polycrystalline silicon. This preliminary step prepares the substrate in advance to promote uniform and controlled crystal growth, reducing the complexity of subsequent processing while achieving the desired larger grain size for improved conductivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces complex mechanical or chemical doping methods with a thermal-crystallization-based approach using a seeding layer. This substitution simplifies the manufacturing process by using controlled thermal fields and material phase transitions rather than complex mechanical interventions to achieve the desired grain structure

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method improves electrical conductivity and performance of memory cells by increasing grain size, enabling higher mobility, current density, and reducing power consumption, thus enhancing read, write, and erase operations.

Implementation Method 1

causing in situ crystal growth in the channel regions

Methodology Applied
Scientific EffectCrystal growth: Crystallisation

Implementation Method 2

using a seeding layer and annealing processes to increase conductivity

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS8933457B23D memory array including crystallized channels
Publication Date: 2015.01.13 MACRONIX INTERNATIONAL CO LTD
  • US8933457B2 patent drawing
  • US8933457B2 patent drawing
  • US8933457B2 patent drawing

AI summary

A method for manufacturing a memory device includes forming a plurality of active layers alternating with insulating layers on a substrate where the active layers include an active material, etching the active layers and insulating layers to define a plurality of stacks of active strips, and after the etching, causing crystal growth in the active strips. The substrate can have a single crystalline surface with a crystal structure orientation, and the crystal growth in the active material can form crystallized material having the crystal structure orientation of the substrate at least near side surfaces of the active strips. Causing crystal growth includes depositing a seeding layer over the plurality of stacks and the substrate, where the seeding layer is in contact with the side surfaces of the active strips, and in contact with the substrate. The method can include, after causing crystal growth, removing the seeding layer.