Fin-FET Memory Gate Sidewall Profile via Two-Step Patterning
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Solution Overview
Problem
Current semiconductor fabrication processes for finFET SG-MONOS devices face challenges in achieving an optimal memory gate sidewall profile, which affects the performance and reliability of embedded memory units in VLSI SOCs.
Innovation Solution
A novel process is developed to fabricate finFET MONOS devices with improved memory gate sidewall profiles by using a two-step patterning process and dielectric films to control the edge surfaces of the memory gate, reducing dopant contamination and ensuring precise alignment and exposure of the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional single-step patterning process is used to form the memory gate, then the fabrication process is simpler and faster, but the memory gate sidewall profile is suboptimal and dopant contamination occurs
Solution Approach 1:
The patterning process is divided into two distinct steps: first forming an upper portion of the memory gate with a specific sidewall profile, then forming a lower portion with different characteristics. This segmentation allows each step to be optimized independently, achieving the desired complex sidewall profile that cannot be obtained through a single patterning step.
Solution Approach 2:
The upper portion of the memory gate is formed first with preliminary patterning to establish the desired sidewall profile. Subsequently, a mask layer is formed and selectively removed to expose specific regions for the second patterning step. This preliminary action enables precise control over where the lower gate portion will be formed, preventing dopant contamination in critical areas.
2Reliability
If the memory gate sidewall profile is not optimized, then the fabrication process is simpler, but dopant contamination is introduced into the charge trap layer
Solution Approach 1:
A mask layer (e.g., mandrel or spacer structure) is introduced as an intermediary element to control the patterning process. This mask layer enables selective exposure of regions during the second patterning step, ensuring that dopants are only introduced where intended and preventing contamination of the charge trap layer while maintaining fabrication feasibility.
Solution Approach 2:
The fabrication process applies different treatments to different regions of the memory gate. The upper portion receives one type of patterning treatment, while the lower portion receives a different treatment through selective mask removal. This local differentiation ensures that critical regions near the charge trap layer are protected from dopant contamination while other regions receive appropriate doping.
3Manufacturing precision
If the select gate and memory gate are not precisely aligned, then the fabrication process is simpler, but the performance of embedded memory units deteriorates
Solution Approach 1:
The select gate structure is formed first as a reference structure, and then the memory gate is patterned in subsequent steps with alignment markers and mask layers that reference the select gate position. This preliminary establishment of the select gate enables precise alignment of the memory gate in later steps, ensuring proper overlapping and electrical connection while maintaining systematic fabrication flow.
Solution Approach 2:
The patent employs advanced lithographic alignment techniques and automated alignment systems that use optical or electronic referencing rather than purely mechanical alignment methods. These systems can precisely locate and align features based on predetermined patterns or markers, achieving sub-micron alignment accuracy without requiring complex mechanical adjustment mechanisms.
Data Source
AI summary
A process is provided to fabricate a finFET device. A gate electrode layer is positioned over a dielectric layer. The gate electrode layer and the dielectric layer are both positioned over and surrounding a fin-shaped semiconductor structure. A gate electrode is formed from the gate electrode layer through a two-step patterning process. At a first patterning step, an upper portion of the gate electrode layer is patterned. Then a dielectric film is formed covering the patterned upper portion of the gate electrode layer. After the dielectric film is formed, a second patterning process is performed to pattern a lower portion of gate electrode layer.