NAND Flash Memory Secure Erase via Overwrite
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Solution Overview
Problem
Current memory systems face inefficiencies in secure erasing operations, particularly in NAND flash memory, where large data amounts lead to prolonged erase times and decreased throughput due to the need for copy operations and extensive erase verification.
Innovation Solution
The implementation of an overwrite program operation that rewrites data to a higher threshold voltage level, eliminating the need for copy operations and allowing for faster secure erasing by converting data into overwrite data, which integrates data into the upper level, making it difficult to read and ensuring security without erasing to the 'Er' level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional erase operations are performed on NAND flash memory, then data is erased to the 'Er' level ensuring complete data removal, but the process requires copy operations and extensive verification leading to prolonged erase times and decreased throughput
Solution Approach 1:
Instead of erasing data to the traditional 'Er' level, the patent inverts the approach by overwriting data to the upper level 'A'. This inversion transforms the erase operation into an overwrite operation that integrates data into the upper level, making it difficult to read while eliminating the need for copy operations and extensive verification, thereby resolving the contradiction between erasure completeness and operation throughput
Solution Approach 2:
The patent changes the threshold voltage parameter from the traditional 'Er' level to the upper level 'A'. By modifying this critical parameter, the system achieves secure erasure through overwrite operations rather than traditional erase operations, reducing operation time and improving throughput while maintaining data security
2Reliability
If traditional erase operations with copy operations are performed, then data security is ensured through complete erasure, but the complexity of copy operations and verification increases device complexity and operation time
Solution Approach 1:
The patent inverts the traditional erase methodology by using overwrite to upper level 'A' instead of erase to level 'Er'. This inversion eliminates the need for copy operations and extensive verification processes, thereby reducing device complexity and operation time while maintaining data security through integration into the upper level
Solution Approach 2:
The patent extracts and eliminates the unnecessary copy operations and extensive verification steps from the traditional erase process. By using overwrite to upper level 'A', the system removes these complex operations while achieving the same security objective, thereby reducing device complexity
3Reliability
If frequent erase operations are performed to maintain data security, then data protection is ensured, but memory cell transistor wear increases reducing effective write and erase cycles
Solution Approach 1:
The patent changes the threshold voltage parameter from 'Er' level to upper level 'A' for secure erasure. This parameter change enables the use of overwrite operations instead of traditional erase operations, which reduces wear on memory cell transistors and extends their effective lifespan while maintaining data protection
Data Source
AI summary
According to one embodiment, a memory system includes a semiconductor memory including a memory cell, and a controller configured to control the semiconductor memory and capable of creating second data based on first data read from the memory cell. Upon receiving a physical erase request for the first data held in the memory cell from an external device, the controller transmits one of an erase instruction and a write instruction for the second data to the semiconductor memory.