3D Memory Device Manufacturing via Selective Etch and Stress Control
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Solution Overview
Problem
The challenge is to manufacture memory devices with a reduced volume and a three-dimensional structure while preventing substrate deformation due to stress differences between thin films during the deposition process.
Innovation Solution
The method involves alternately stacking insulation and sacrificial layers on a substrate, forming through holes and openings, and using an etchant to remove the sacrificial layer, with specific gas selections for silicon oxide deposition and etching, including SiH4, Si2H6, Si3H8, Si4H10, and dichlorosilane, to achieve etch selectivity and minimize substrate deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple thin films are deposited on the substrate to create a three-dimensional structure, then the memory device capacity is improved, but the substrate deforms due to stress difference between the thin films
Solution Approach 1:
The patent changes the physical and chemical parameters of the deposited films by controlling deposition conditions (temperature, pressure, gas flow rates) to adjust film stress characteristics. This allows the accumulation of multiple thin films for increased capacity while managing substrate deformation through parameter optimization
Solution Approach 2:
The patent applies different deposition parameters to different regions or layers of the thin film structure. By locally controlling deposition conditions for each layer, the stress distribution across the multi-layer structure is optimized, preventing substrate deformation while maintaining high device capacity
2Ease of manufacture
If conventional planar structure is used, then the manufacturing process is simple, but the memory device volume is large and integration degree is low
Solution Approach 1:
The patent transitions from a conventional planar (two-dimensional) structure to a three-dimensional structure by stacking multiple thin films vertically. This dimensional change increases the integration degree and reduces device volume while maintaining manufacturability through controlled deposition processes
3Shape
If etchant is supplied to remove the sacrificial layer, then the three-dimensional structure is formed, but the insulation layer may be damaged
Solution Approach 1:
The patent applies different material compositions to different functional layers. The insulation layer contains carbon atoms that provide etch selectivity, making it resistant to the etchant used to remove the sacrificial layer. This local material differentiation protects the insulation layer while enabling three-dimensional structure formation
Solution Approach 2:
The patent uses composite material composition in the insulation layer (containing silicon, oxygen, and carbon atoms) to achieve both structural integrity and etch resistance. The composite nature of the insulation layer provides selective protection during the etching process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of a three-dimensional memory device structure that reduces volume and prevents substrate deformation, enabling efficient manufacturing with effective removal of sacrificial layers and minimizing damage to insulation layers.
Implementation Method 1
the stacking of the insulation layer includes supplying at least one gas selected from the group including SiH4, Si2H6, Si3H8, and Si4H10 onto the substrate to deposit a first silicon oxide, and the stacking of the sacrificial layer includes supplying dichlorosilane (SiCl2H2) onto the substrate to deposit a second silicon oxide
Implementation Method 2
supplying an etchant through the opening to remove the sacrificial layer, wherein the insulation layer and the sacrificial layer may have etch selectivity with respect to the etchant, and the sacrificial layer may have an etch rate greater by about 5 times to about 300 times than that of the insulation layer
Data Source
AI summary
A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiCl2H2) to the substrate.