Solid-State Devices TRIZ Cases

OLED display panel substrate through holes route light directly to the sensing unit.

An array substrate with point light sources and photosensors prevents valley ridge interference by illuminating specific regions sequentially.

Multi-layer transistors expand capacitor area without enlarging pixel footprint, retaining voltage against leakage currents in high-definition displays.

A p-i-n image sensor array uses hybrid bonding to join the detector to the read-out integrated circuit.

A cylindrical core surrounded by stacked magnetic layers uses the Spin Hall Effect to switch magnetization for data storage.

Movable bases adjust spacing via distance components to resolve low precision in Micro LED manufacturing.

Holes in the peripheral metal layer channel melted sealing material away from the bonding interface, preventing accumulation that causes partial detachment.

Atomic diffusion bonding connects semiconductor electrodes to interconnect terminals using continuous metal layers.

Dielectric deposition within trenches prevents resist collapse caused by capillary forces, ensuring precise feature formation.

Two-mask lithography segments contact formation to reduce alignment errors and fabrication costs in sub-16nm FinFET arrays.

A boron-doped rare-earth oxide nonmagnet enables perpendicular magnetic anisotropy, reducing write current and enhancing thermal stability.

Blocking pocket implants in the diode reduces junction capacitance, enabling faster turn-on times and improved electro-static discharge protection.

A lens assembly integrates a blue glass filter member to absorb infrared light and correct chromatic aberration.

Segmenting InGaN into discrete nanowires reduces lattice mismatch, maintaining high internal quantum efficiency at longer wavelengths.

A micro-cavity structure with reflective anode and transflective cathode electrodes manages photoluminescence and electroluminescence peak differences across red, green, and blue sub-pixels.

Peripheral trenches and ring-shaped metallization reduce lateral light emission while improving electric injection efficiency for LED microchips.

Bonding a frame member to a package holds the light-transmissive member, preventing cracks from thermal expansion differences.

Gap filling layers shield ion injection target layers from foreign substance contamination during deep hole formation, preventing defective junctions.

A dual-sided display integrates bottom emission and top emission LEDs on a single substrate to generate images in opposite directions.

A U-shaped bottom electrode increases the effective area of a ferroelectric random access memory structure.

High-permittivity dielectric layers reduce local electric fields near electrodes, preventing electrical conduction in chip-scale isolators.

Nanoscale hygroscopic particles maintain transparency and adhesion while preventing water intrusion.

Self-aligned source drain formation precedes gate stack creation, protecting integrity and reducing complexity in advanced CMOS nodes.

Selective etching removes sacrificial layers while parameter-controlled deposition prevents substrate deformation during 3D memory manufacturing.

A touch panel uses carbon nanotube layers for electrodes to achieve high sensitivity and accuracy.

Magneto-electric spin orbit logic replaces CMOS components with multi-functional MESO devices, reducing energy consumption to 10 attojoules per switching event.

Segmenting and merging dual-side functions into one substrate reduces thickness while maintaining transparency.

A maskless patterning method uses semiconductor partition walls to define color conversion layers on micro-LED arrays.

A display device uses a segmented seal pattern to decrease bezel width while maintaining substrate rigidity.

Alternating logic circuits by power supply enables common diffusion layers, reducing layout area while lowering standby current consumption.

Segmenting pixels with a high-k dielectric grid reduces destructive interference, improving quantum efficiency while maintaining integration density.

A fluorinated amorphous layer coats mesa photodiode side surfaces to suppress dark current generation at the interface.

A liquid crystal display manufacturing method uses pixel electrodes as masks to form source and drain electrodes.

Selective etching of a third insulating layer enables planarization of precursor layers for organic EL pixel electrodes.

Varying isolation trench depths via embedded etching stop features reduces etching damage and improves electrical isolation in scaled-down image sensor devices.

A method for manufacturing light emitting devices using a gallium-face substrate to form semiconductor layers.

Double-sided capacitor attachment on lead frame leads reduces sensor package thickness while meeting electromagnetic compatibility requirements.

Merging gate electrodes minimizes the common region to shrink transistor dimensions while LDD regions suppress off current.

Resonator structures induce photoconductivity in a substrate to detect electromagnetic radiation.

Shielded light detectors isolate photodiodes to minimize crosstalk, optimizing signal-to-noise ratio for high-resolution distance imaging.

A thin glass substrate encapsulation structure with an out-coupling film and getter layer enhances organic light emitting device performance.

Incorporates a side surface inclined portion with light-transmitting resin to guide emitted light outward from the semiconductor chip.

A mini LED backlight panel uses fluorescent powder or quantum dots in splicing gaps to fill optical discontinuities between sub-panels.

Silyl groups replace weak hydrogen bonds with covalent links, resolving heat stability issues in photovoltaic elements.

Segmented green sub-pixel emission layers optimize electron-hole recombination through distinct hole host and dopant regions, reducing energy loss.

Selective etching of insulating layers creates a groove that simplifies contact hole formation and reduces manufacturing costs.

A structured memory element with distinct material regions forms a capacitive voltage divider to stabilize polarization states in ferroelectric devices.

Conductive oxide semiconductor films increase pixel aperture ratio, resolving the trade-off between silicon manufacturability and luminance.

Incorporating a borane compound into charge transport layers improves initial voltage and quantum efficiency while maintaining simple device architecture.

TaFISA deposits aligned carbon nanotube films at a liquid interface for scalable electronics.