Integrated Gate Electrodes for Small Thin Film Transistors
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Solution Overview
Problem
The size of thin film transistors in active matrix liquid crystal display devices is limited by inconsistencies in gate electrode sizes and photolithographic technology, making it difficult to form small transistors with low off current.
Innovation Solution
The gate electrodes of first and second thin film transistors are integrated, allowing for the formation of small transistors with a common region and LDD regions, which reduces the size of the common region and minimizes off current by optimizing the semiconductor layer structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If separate gate electrodes are formed for first and second thin film transistors, then manufacturing precision can be maintained, but transistor size cannot be reduced below approximately 5 μm due to processing inconsistencies and photolithographic limitations
Solution Approach 1:
The patent merges the gate electrodes of the first and second thin film transistors into a single common gate electrode structure. This integration eliminates the need for separate gate electrode formation processes, thereby removing the accumulation of processing inconsistencies and photolithographic limitations that previously constrained transistor size to approximately 5 μm or larger. The unified gate electrode allows for smaller transistor dimensions while maintaining manufacturing precision.
2Area of moving object
If the common region length is reduced to minimize transistor size, then transistor area decreases, but off current increases due to insufficient field control
Solution Approach 1:
The patent applies local quality by introducing LDD regions with specifically engineered impurity concentrations in the semiconductor layer adjacent to the drain and source regions. These LDD regions create a gradual impurity concentration gradient that locally modifies the electric field distribution, effectively lowering peak field concentrations without requiring a large common region. This allows for reduced transistor area while maintaining sufficient field control to suppress off current.
Solution Approach 2:
The patent changes the impurity concentration parameter in the semiconductor layer by forming LDD regions with lower impurity concentrations compared to the channel region. This parameter modification creates a controlled electric field profile that reduces peak field strength in critical areas, enabling smaller transistor dimensions while maintaining adequate off-state current suppression through optimized field distribution rather than relying solely on geometric dimensions.
Data Source
AI summary
A display device is provided in which at least first and second thin film transistors are formed on a substrate, including a gate electrode formed on a semiconductor layer with a gate insulating film in between. The semiconductor layer is divided into individual regions for each film transistor, and is provided with a common region and LDD regions between a channel region and a drain region, as well as between the channel region and a source region. The gate electrode is formed as an integrated gate electrode for the first and second thin film transistors that faces the common region, the channel region and the LDD regions of the first thin film transistor and the channel region and the LDD regions of the second thin film transistor.