Semiconductor Device Manufacturing via Atomic Diffusion Bonding
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Solution Overview
Problem
Conventional semiconductor chip mounting on a mounting board requires individual bumps for each electrode, increasing manufacturing time and cost, thus lowering productivity.
Innovation Solution
A method involving atomic diffusion bonding or surface activated joining to electrically connect semiconductor elements to a base with interconnect terminals without the need for individual bonding members, using metal layers to facilitate connection and insulating or removing excess metal layers to prevent short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual bumps are provided for each electrode of the semiconductor chip, then reliable electrical connection is achieved, but manufacturing time increases and productivity decreases
Solution Approach 1:
The patent merges multiple individual bump formation processes into a single continuous metal layer formation process. The continuous metal layer is formed to simultaneously cover multiple electrodes and interconnect terminals, eliminating the need for separate bump formation for each electrode. This combining approach maintains electrical connection reliability while significantly reducing manufacturing steps and improving productivity.
Solution Approach 2:
The continuous metal layer serves multiple functions simultaneously: it provides electrical connection for multiple electrodes, acts as a bonding surface for atomic diffusion bonding, and can be selectively removed or insulated in specific regions. This multi-functional design replaces the need for individual bumps at each electrode location, resolving the contradiction between connection reliability and manufacturing efficiency.
2Productivity
If a continuous metal layer is formed to cover multiple electrodes, then manufacturing process is simplified and productivity improves, but risk of short-circuiting between adjacent electrodes increases
Solution Approach 1:
The patent applies local quality by selectively removing or rendering electrically insulative the continuous metal layer in specific regions. The metal layer is removed or insulated in the third portion that lies outside the first portion (between first electrode and first interconnect terminal) and second portion (between second electrode and second interconnect terminal). This localized modification maintains electrical connection where needed while preventing short-circuits in regions where the continuous layer would cause harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the need for individual bonding members, enhancing productivity by simplifying the manufacturing process and preventing short-circuiting, thereby improving the efficiency of semiconductor device production.
Implementation Method 1
providing electrical connection between the first electrode and the first interconnect terminal as well as between the second electrode and the second interconnect terminal, by atomic diffusion bonding
Data Source
AI summary
A method for manufacturing a semiconductor device includes: providing a support with a semiconductor light-emitting element including a first electrode and a second electrode; providing a base including a first interconnect terminal and a second interconnect terminal; forming a first metal layer on the support to cover the first and the second electrodes; forming a second metal layer on the base to cover the first and the second interconnect terminals; arranging the first and second electrodes and the first and second interconnect terminals to respectively face each other, and providing electrical connection therebetween by atomic diffusion; and rendering electrically insulative or removing portions of the first metal layer and the second metal layer that are outside thereof defined between the first and second electrodes and the first and second interconnect terminals.