Semiconductor Layout Design Using Common Diffusion Layers
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Solution Overview
Problem
In semiconductor devices with logic circuits driven by different power supply lines, the existing layout designs fail to reduce the layout area effectively when adjacent circuits are connected to different power supply systems, as they require different potentials, preventing the formation of common diffusion layers.
Innovation Solution
The semiconductor device layout is optimized by alternately arranging logic circuits connected to identical power supply lines, allowing for the sharing of diffusion layers between adjacent transistors, which reduces the layout area by using common diffusion layers for adjacent MOS transistors connected to the same power source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If logic circuits are arranged adjacently with different power supply lines, then power consumption is reduced through alternating power systems, but layout area cannot be reduced due to inability to form common diffusion layers
Solution Approach 1:
The layout is segmented into odd-numbered logic circuits connected to a first power supply and even-numbered logic circuits connected to a second power supply. This segmentation allows adjacent circuits with different power supplies to be arranged alternately while maintaining the ability to form common diffusion layers within each power supply group, thus reducing layout area while achieving power consumption reduction.
2Area of stationary object
If common diffusion layers are formed for adjacent transistors, then layout area is reduced, but this requires adjacent circuits to be connected to the same power supply line
Solution Approach 1:
Diffusion layers of transistors in odd-numbered logic circuits are merged to form common diffusion layers connected to the first power supply, and diffusion layers of transistors in even-numbered logic circuits are merged to form common diffusion layers connected to the second power supply. This merging approach enables layout area reduction while accommodating different power supply configurations through alternating arrangement.
3Loss of energy
If adjacent logic circuits are connected to different power supply lines, then current consumption in standby mode is reduced, but diffusion layers cannot be shared between adjacent transistors
Solution Approach 1:
The circuit is segmented into odd-numbered logic circuits and even-numbered logic circuits that are alternately arranged. Each segment shares common diffusion layers within its power supply group (first power supply for odd circuits, second power supply for even circuits), enabling both standby current reduction through different power supplies and diffusion layer sharing within segments.
Data Source
AI summary
A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.