Finfet SRAM Strapped Contact Two-Mask Process
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Solution Overview
Problem
Traditional SRAM array fabrication at sub-16 nm technology nodes faces challenges with alignment errors and increased costs due to the complex multi-mask patterning processes required for etching contacts to source and drain regions, which complicates the integration and scalability of transistor features.
Innovation Solution
A two-mask process is implemented to form strapped contacts by etching trenches through an interlayer dielectric to expose fins and filling them with metal, reducing the number of masks needed and thereby minimizing alignment errors and costs, while extending the source/drain regions of multiple transistors in a small die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a four-mask process is used to etch contacts for transistor source and drain regions in sub-16 nm technology nodes, then the contacts can be formed with complex device integration, but the number of lithography prints increases and alignment errors are more likely to occur
Solution Approach 1:
The patent segments the contact formation process into two distinct mask steps rather than four. The first mask forms initial contact holes, and the second mask forms the remaining contact holes and straps. This segmentation reduces the total number of lithography prints from four to two, directly addressing the contradiction by simplifying the process while maintaining alignment precision through fewer overlay operations.
Solution Approach 2:
The patent merges the formation of multiple contact holes and straps into a consolidated two-mask process. Instead of separately patterning each contact hole with individual masks, the invention combines the patterning of multiple contacts and interconnect straps into just two lithography steps, reducing process complexity while achieving the same functional outcome.
2Ease of manufacture
If four masks are used to etch contacts, then complete coverage of source and drain regions can be achieved, but fabrication costs increase due to multiple lithography prints
Solution Approach 1:
The patent segments the lithography process into two strategic steps rather than four sequential prints. The first mask step patterns initial contact holes, and the second mask step patterns remaining contacts and interconnect straps. This segmentation reduces material consumption (photoresist, mask layers) and fabrication costs by eliminating two complete lithography cycles while maintaining complete coverage of all required contact regions.
Solution Approach 2:
The second mask in the patent serves multiple functions simultaneously: it forms remaining contact holes and creates interconnect straps that provide electrical connections between multiple transistors. This multi-functionality reduces the total number of lithography prints required, directly addressing the cost issue by making each lithography step more efficient and reducing the quantity of lithography materials needed.
3Reliability
If multiple masks are overlaid to perform different etches, then various contact regions can be accessed, but the likelihood of alignment errors increases
Solution Approach 1:
The patent segments the contact formation into two mask steps, reducing the number of overlay operations from three (in a four-mask process) to just one (in a two-mask process). Each mask step is strategically designed to form specific contact holes, and the reduced number of overlays directly decreases the cumulative alignment error rate, improving reliability.
Solution Approach 2:
The patent uses strategically positioned interconnect straps as intermediaries that simplify the masking process. These straps serve as alignment references and electrical connectors, reducing the need for multiple precise overlay operations. By using these intermediary structures, the process achieves reliable alignment with fewer mask steps.
Data Source
AI summary
An apparatus includes a first fin (116) of a first transistor and a second fin (118) of a second transistor. The apparatus also include a first contact (138) coupled to the first fin and a second contact (142) coupled to the second fin. The apparatus further includes a strapped contact (164) coupled to the first contact and to the second contact.