3D Memory Cell Stacking With Self-Aligned Interlayer Bonding
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Solution Overview
Problem
Current 3D semiconductor chip technologies face challenges in constructing high-density connections between layers due to misalignment issues and high-temperature processing, which degrade wiring and transistor reliability, limiting connectivity and performance.
Innovation Solution
A method for producing 3D semiconductor devices involving the use of single crystal transistors and oxide-to-oxide bonding, with self-aligned lithography and etching processes to form multiple levels of transistors and memory cells, allowing for precise alignment and reduced thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing (>700°C) is used to construct transistors in 3D stacking, then transistor performance is improved, but wiring layers are damaged due to temperatures exceeding 400°C
Solution Approach 1:
The patent divides the 3D stacking process into separate stages: first constructing transistor layers at high temperature, then adding wiring layers at lower temperature in subsequent processing steps. This segmentation allows each component to be fabricated under optimal conditions without interfering with the other.
Solution Approach 2:
The transistor layers are constructed in advance before the wiring layers are formed. By completing the high-temperature transistor fabrication first and protecting it with intermediate layers, the subsequent low-temperature wiring processes can proceed without damaging the transistors.
2Ease of manufacture
If conventional lithographic alignment is used in 3D stacking, then manufacturing simplicity is maintained, but misalignment errors limit connectivity density between layers
Solution Approach 1:
The patent implements self-aligned lithography where alignment marks are automatically generated from the transistor patterns themselves, and the lithographic system uses these marks to automatically position subsequent layers. This eliminates manual alignment operations while achieving sub-40nm precision.
Solution Approach 2:
The patent replaces mechanical alignment methods with optical field-based alignment using lithographic projection. Alignment marks are projected optically onto the photoresist layer, enabling precise positioning without physical contact or manual intervention.
3Ease of operation
If through-silicon via (TSV) technology is used for interlayer connections, then vertical connectivity is achieved, but contact size must be large and connection density is limited
Solution Approach 1:
The patent transitions from vertical TSV connections to lateral planar connections within each layer, then uses multiple closely-spaced layers for vertical connectivity. This dimensional approach allows much higher connection density since planar routing offers more freedom than vertical drilling through silicon.
Solution Approach 2:
The patent nests multiple transistor and wiring layers within each other in a compact vertical stack, with each layer containing high-density connections. The layers are tightly integrated with minimal spacing, achieving high overall connection density without requiring large individual contact areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-density connectivity and improved reliability of 3D semiconductor devices by minimizing misalignment errors and maintaining transistor performance across multiple layers.
Implementation Method 1
oxide-to-oxide bonding
Data Source
AI summary
A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the first level includes control of power delivery to the at least one third transistor.