3D Stacked Memory Subarrays With Shared Bit Lines
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high storage density and process margin for word lines due to complex manufacturing processes and limited space for forming through-silicon vias, which restrict die size scaling and increase manufacturing costs.
Innovation Solution
The implementation of super vias that extend through multiple conductive layers, allowing for stacked memory subarrays to share a common bit line, reducing manufacturing complexity and increasing process margins for word lines, while also forming vias during the wafer manufacturing process to simplify production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-silicon vias are formed to achieve high storage density, then storage density is improved, but manufacturing complexity increases and process margin decreases
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional stacked structures. Multiple memory subarrays are stacked vertically along a first direction, with bit lines positioned between stacked memory cell rows. This vertical stacking enables higher storage density without requiring additional through-silicon vias, as connections are established through the stacked architecture itself rather than through complex via structures.
Solution Approach 2:
The bit line structure serves multiple functions: it acts as a common bit line for multiple memory subarrays, provides electrical connection between stacked memory cell rows, and eliminates the need for separate through-silicon via structures. This multi-functional design reduces manufacturing complexity while maintaining high storage density.
2Quantity of substance
If through-silicon vias are formed to increase storage density, then storage density is improved, but die size scaling is restricted
Solution Approach 1:
The invention moves memory storage from a two-dimensional planar layout to a three-dimensional stacked configuration. Memory subarrays are arranged vertically, allowing the die to maintain a compact footprint while achieving higher storage density through the additional vertical dimension. This eliminates the need to increase die size to accommodate more storage capacity.
3Quantity of substance
If through-silicon vias are formed to achieve high storage density, then storage density is improved, but manufacturing costs increase
Solution Approach 1:
The patent extracts and eliminates the through-silicon via formation process from the manufacturing sequence. By using stacked memory subarrays with shared bit lines, the design removes the need for complex via formation, filling, and alignment steps that typically increase manufacturing costs. The simplified structure reduces process steps and associated costs.
4Ease of manufacture
If conventional memory structures are used, then manufacturing process is simpler, but RC delay increases and data operation speed decreases
Solution Approach 1:
The stacked memory structure positions bit lines vertically between memory cell rows, significantly shortening the horizontal distance that bit lines must traverse. This vertical arrangement reduces the bit line length and associated RC delay compared to conventional planar structures, enabling faster data operation speeds while maintaining manufacturing feasibility.
Data Source
AI summary
Systems, devices, and manufacturing methods of a semiconductor device are provided. In one aspect, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a memory array. The memory array includes a first memory subarray and a second memory subarray stacked along a first direction. A first row of memory cells of the first memory subarray and a first row of memory cells of the second memory subarray are coupled to a same bit line. The same bit line is between the first memory subarray and the second memory subarray along the first direction. The second semiconductor structure includes a control circuitry coupled to the memory array. The semiconductor device includes a second via structure that is coupled to the pad-out structure of the second semiconductor structure through the first via structure and the interconnection structure.