3D Memory Shielding Layer for Signal Integrity
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Solution Overview
Problem
In 3D memory devices, the stacked architecture leads to increased noise and signal distortion due to extra capacitance and resistance from additional metal routing, causing coupling effects between periphery circuits and memory arrays, which exacerbates signal integrity issues during operation.
Innovation Solution
A shielding layer with a conduction region is introduced between the stacked periphery circuits and memory array, receiving a grounding voltage to reduce or eliminate the coupling effect by shielding electrical energy transfer between metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a stacked 3D memory architecture is used to increase memory density, then memory capacity is improved, but signal distortion and noise increase due to extra capacitance and resistance from additional metal routing
Solution Approach 1:
A shielding layer is introduced as an intermediary component between the memory array and peripheral circuits. This shielding layer includes a conduction region configured to receive a grounding voltage, which mediates the electromagnetic coupling between stacked components. The shielding layer acts as a buffer that blocks harmful electromagnetic interference while allowing the stacked architecture to maintain its high density benefits.
2Quantity of substance
If additional metal routing layers are added to support stacked architecture, then memory capacity is improved, but capacitance and resistance increase causing noise and signal distortion
Solution Approach 1:
The shielding layer serves as an intermediary that blocks electromagnetic coupling between the memory array and peripheral circuits. By placing this conductive shield with grounding voltage between the two functional blocks, the patent prevents noise and signal distortion from propagating through the additional metal routing layers, while still allowing the stacked architecture to achieve high memory capacity.
3Device complexity
If periphery circuits are stacked close to memory arrays to save space, then device integration is improved, but coupling effects between circuits and arrays increase exacerbating signal integrity issues
Solution Approach 1:
The shielding layer is positioned between the memory array and peripheral circuits in the stacked architecture. This intermediary conductive layer with grounding voltage effectively decouples the electromagnetic fields of adjacent components, allowing high device integration with peripheral circuits placed close to the memory array without suffering from harmful coupling effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shielding layer effectively reduces signal distortion and maintains signal integrity by minimizing the coupling effect between interconnects in 3D memory devices during operation.
Implementation Method 1
A shielding layer with a conduction region is introduced between the stacked periphery circuits and memory array, receiving a grounding voltage to reduce or eliminate the coupling effect by shielding electrical energy transfer between metal interconnects.
Implementation Method 2
The shielding layer includes a conduction region configured to receive a grounding voltage during operation of the 3D memory device.
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a substrate. A first interconnect layer including a first plurality of interconnects is formed above the peripheral device. A shielding layer including a conduction region is formed above the first interconnect layer. A second interconnect layer including a second plurality of interconnects is formed above the shielding layer. The conduction region of the shielding layer covers an area of the first and second plurality of interconnects in the first and second interconnect layers. A plurality of memory strings each extending vertically above the second interconnect layer are formed.