3D Memory Gate Line Slit Layout for Wafer Stability
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Solution Overview
Problem
Planar memory cells face density limitations and structural instability issues as feature sizes approach a lower limit, leading to challenges in manufacturing 3D NAND memory devices due to wafer deformation and increased etch depth of gate line slits, which can cause memory finger collapse and overlay errors.
Innovation Solution
A 3D memory device design featuring alternating conductive/dielectric stacks with staggered gate line slit structures, including first and second type GLS portions, to enhance structural stability and reduce the risk of collapse, while maintaining storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of film layers is increased to improve area utilization, then storage capacity is improved, but wafer deformation occurs due to film stresses
Solution Approach 1:
The gate line slits are divided into two types: first type GLS portions that penetrate the alternating conductive/dielectric stack completely, and second type GLS portions that are located in the upper portion only. This segmentation allows different regions of the stack to have different structural characteristics, reducing overall stress while maintaining storage capacity.
Solution Approach 2:
Different portions of the gate line slits have different structural properties. The first type GLS portions provide complete penetration for electrical isolation, while the second type GLS portions in the upper portion reduce stress concentration. This local differentiation of structural quality resolves the contradiction between storage capacity and wafer stability.
2Quantity of substance
If the number of oxide/nitride layers is increased to improve density, then storage capacity is improved, but etch depth of gate line slit increases causing structural instability
Solution Approach 1:
The gate line slits are segmented into first type portions extending through the full stack and second type portions in the upper portion only. This segmentation reduces the continuous etch depth required compared to traditional complete penetration slits, thereby improving structural stability while maintaining the ability to isolate memory fingers.
Solution Approach 2:
The upper portion of the stack contains second type GLS portions with reduced etch depth, while the lower portion contains first type GLS portions providing complete isolation. This local quality differentiation allows the structure to maintain reliability by reducing stress in the upper regions where memory fingers are most vulnerable to collapse.
3Quantity of substance
If feature sizes are reduced to increase density, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The gate line slits are segmented into two types with different geometries, allowing optimization of each portion for its specific function. This segmentation enables the structure to achieve high density without proportionally increasing fabrication complexity, as each segment can be formed using adapted versions of existing processes.
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive/dielectric stack on a substrate, a plurality of channel structures in the alternating conductive/dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive/dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive/dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive/dielectric stack.