3D Memory Source Layer Structure to Prevent Arcing
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving manufacturing stability and increasing the degree of integration, particularly in three-dimensional (3D) semiconductor memory devices, where the complexity of stacked structures and high power applications can lead to arcing and process inefficiencies.
Innovation Solution
The semiconductor memory device incorporates a gate stacked body, insulating layers, and source layers with protrusions and grooves to manage charge distribution and prevent arcing during manufacturing, allowing for increased integration and stability by using a first source layer with lower resistivity and a second source layer with doped semiconductor material, enabling efficient channel structure penetration and contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells is increased to improve integration density, then the degree of integration is improved, but the complexity of the stacked structure increases leading to manufacturing instability and arcing
Solution Approach 1:
The source layer is divided into multiple segments: a first source layer, a second source layer with a groove, and a third source layer. This segmentation reduces the complexity of the stacked structure by breaking it into manageable sections, each with specific functions, thereby preventing manufacturing instability and arcing while maintaining high integration density.
Solution Approach 2:
The second source layer includes a groove at a specific location to form a contact hole, creating local variation in structure. This local quality change allows for proper electrical contact formation in high-density stacked structures without compromising overall manufacturing stability, resolving the contradiction between integration density and structural complexity.
2Productivity
If high power is applied during manufacturing to improve process efficiency, then productivity is improved, but arcing occurs leading to manufacturing instability
Solution Approach 1:
The second source layer with the groove is formed in advance before the gate stacked body is fully assembled. This preliminary action ensures that contact holes are pre-positioned correctly, allowing for stable manufacturing processes even when high power is applied, thereby preventing arcing while maintaining productivity.
Solution Approach 2:
The groove in the second source layer acts as an intermediary structure that facilitates proper electrical contact formation. This intermediate feature enables stable manufacturing by providing a controlled path for electrical connections, preventing arcing during high-power processing while maintaining manufacturing efficiency.
Data Source
AI summary
A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stacked body, an insulating layer overlapping the gate stacked body, a first source layer including a horizontal portion between the gate stacked body and the insulating layer and a protrusion extending from the horizontal portion so as to penetrate the insulating layer, a channel layer penetrating the gate stacked body and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stacked body, and a second source layer disposed between the gate stacked body and the first source layer and coming in contact with the channel layer.