3D Semiconductor Memory Stack With Multi-Material Source Layers
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Solution Overview
Problem
Existing two-dimensional semiconductor devices face limitations in integration due to the need for expensive processing equipment to achieve fine patterns, which hinders their ability to store large amounts of data efficiently.
Innovation Solution
A three-dimensional semiconductor memory device with a stack structure of alternately stacked interlayer insulating layers and gate electrodes, featuring vertical channel structures and source conductive patterns of different materials, allowing for improved electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are used to increase integration, then data storage capacity can be improved, but expensive processing equipment is needed to achieve fine patterns which increases manufacturing cost and limits further integration
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory layers are stacked in the vertical direction, allowing data storage capacity to scale with the number of layers rather than requiring continuous reduction of feature sizes in a single plane. This dimensional change enables continued capacity growth without proportionally increasing manufacturing complexity.
2Manufacturing precision
If pattern fineness is increased to improve integration of two-dimensional devices, then data storage capacity improves, but expensive processing equipment is required which sets a practical limitation
Solution Approach 1:
Instead of continuously reducing feature sizes in two dimensions which requires increasingly sophisticated lithography equipment, the patent stacks multiple memory layers vertically. This allows integration to scale with the number of stacked layers rather than requiring ever-finer patterns, thereby avoiding the need for exponentially more expensive processing equipment.
Solution Approach 2:
The memory device is divided into multiple discrete stacked layers, each containing memory cells. This segmentation allows the overall integration to be achieved through stacking simpler, identical or similar layers rather than creating increasingly complex single-layer patterns, reducing the demand for ultra-fine pattern processing equipment.
3Quantity of substance
If three-dimensional semiconductor memory devices are proposed to overcome two-dimensional limitations, then data storage capacity per unit area improves, but device complexity increases
Solution Approach 1:
The patent achieves higher data storage capacity per unit area by stacking memory layers in the vertical dimension. Each layer can be structured similarly to conventional planar memory cells, but the vertical stacking multiplies the effective storage capacity without proportionally increasing the planar footprint or the complexity of individual cell structures.
Solution Approach 2:
The stacked memory layers use similar or identical structures for data storage across all layers, with shared control mechanisms such as word lines and bit lines that extend through multiple layers. This universality allows the same design to be replicated vertically, increasing capacity without proportionally increasing the complexity of controlling and accessing the memory cells.
Data Source
AI summary
A three-dimensional semiconductor memory device is provided. The memory device includes a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure and including a cell array region and a cell array contact region. The cell array structure includes a stack structure including alternately stacked interlayer insulating layers and gate electrodes, a first source conductive pattern, a second source conductive pattern, and a third source conductive pattern sequentially stacked on the stack structure. The first to third source conductive patterns include different materials from each other. Vertical channel structures extending into a lower portion of the first source conductive pattern through the stack structure is included. The first to third source conductive patterns extend from the cell array region to the cell array contact region. The vertical channel structures include vertical semiconductor patterns that contact to the first source conductive pattern.