3D Semiconductor Memory Device Source Layer Architecture
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Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices require complex processes and are challenging to manufacture due to the need for pipe transistors and difficulty in controlling threshold voltages, as well as issues with etching memory layers in high aspect ratio channel holes, which can damage the memory layer and deteriorate cell characteristics.
Innovation Solution
A semiconductor device and manufacturing method that eliminate the need for pipe transistors by forming semiconductor pillars with a first source layer, second source layer, and third source layer, where the third source layer is coupled to the first and second source layers, reducing source resistance and simplifying the manufacturing process by avoiding the etching of memory layers on bottom surfaces of channel holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipe transistors are used to couple source side and drain side memory cells, then memory cells can be connected vertically, but the number of manufacturing processes increases and threshold voltage control becomes difficult
Solution Approach 1:
The patent removes the pipe transistor component from the memory string structure. Instead of using separate pipe transistors to couple source and drain side memory cells, the invention integrates the coupling function directly into the source layer structure, eliminating the need for additional pipe transistor formation processes and simplifying the overall device architecture
Solution Approach 2:
The patent merges the source layer with the channel hole structure by forming the source layer at the bottom of the channel holes and coupling it with the first source layer through the second source layer. This integration combines previously separate components (source layer and channel structure) into a unified structure, reducing manufacturing complexity while maintaining vertical connectivity
2Ease of operation
If memory layer is etched on bottom surfaces of channel holes to expose source region, then source region can be accessed, but memory layer damage occurs and cell characteristics deteriorate
Solution Approach 1:
Instead of etching away the memory layer to expose the source region, the patent inverts the approach by forming the source layer directly at the bottom of the channel holes and coupling it with the first source layer through the second source layer. This eliminates the harmful etching process while still achieving source region accessibility through the coupled source layer structure
Solution Approach 2:
The patent introduces the second source layer as an intermediary structure that couples the first source layer with the source region at the bottom of channel holes. This intermediary structure provides a pathway for electrical connection without requiring direct exposure or etching of the memory layer, thereby preserving memory layer integrity while enabling source region access
Data Source
AI summary
A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.