Transistor TRIZ Cases

Nitrogen plasma treatment forms crystalline source and drain regions in oxide semiconductor transistors to reduce contact resistance.

A dual-gate MOSFET structure with varied well impurity concentrations enhances electrical conductivity parameters.

Non-selective epitaxial growth deposits a buried SiGe channel and cap layer, reducing short-channel effects while maintaining high carrier mobility.

A solid-state image sensor applies control and bias voltages to a generated-charge retention gate portion.

A fuse structure uses a metal element and thin film resistor to break circuits during electrical overstress events.

Segmenting the charge storage layer into a main body and tip allows separate programming and erase paths, reducing voltage while enhancing write reliability.

A hydrogen-containing top electrode enables annealing processes that passivate silicon dangling bonds at the interface.

A unified insulating layer functions as both gate oxide and dielectric in a semiconductor transistor structure.

N2O plasma alters damaged interfaces between IGZO channels and passivation layers, boosting thermal bias stress resistance.

A low ohmic current path connects back-surface metallization to control electrodes, reducing manufacturing complexity and cost.

Plasma treatment forms conductive ohmic contact layers on thin film transistor substrates without ion doping.

Transition metal dichalcogenide assemblies integrate two-dimensional layers onto flexible substrates to create resilient transistor channels.

Group III-nitride transistors resolve the breakdown voltage versus gain cutoff frequency contradiction to integrate power management and RF circuits.

A semiconductor device uses a charge discharge circuit to control gate voltage during overcurrent events.

Segmented unit bipolar transistors prevent latch-up in high-voltage integrated circuits, reducing circuit area compared to large-area diodes.

A semiconductor substrate layer structure absorbs minority carriers to minimize leakage current in the charge storage region.

A configurable dual-channel 3D resurf drain extended MOSFET integrates lateral drift lanes and cascode transistors.

A semiconductor apparatus incorporates a diode between trench gate electrodes to manage electrical signals.

Metal thioacetate additives in the solution inhibit crystalline formation, enabling stable amorphous oxide semiconductors with high charge mobility.

Segmented silicon and germanium channels maintain threshold voltage stability in vertical 3D memory despite shrunk design rules.

Controlling fin height below 400 angstroms eliminates STI residues, maintaining drive current without performance loss.

A tuneable diffusion resistor uses a varactor structure to adjust resistance via voltage-controlled depletion regions.

A dielectric fuse memory circuit uses gate dielectric breakdown to change conductivity states for stable information storage.

Multiple storage nodes in a single pixel store image charges from different exposure times, enabling high dynamic range imaging without readout delays.

A trench MOSFET integrates a lightly doped source region to form an adjustable contact source ballast resistor within the device structure.

Metallic conductive structures in local interconnection layers provide precise resistance values within semiconductor integrated circuits.

Vertical depleted SCR structure reduces capacitance while minimizing area occupancy in integrated circuit protection.

A non-planar transistor structure with a self-aligned silicide interconnect electrically couples a trench capacitor to the channel region.

Selective etch process forms high-k dielectric metal gate stacks after transistor fabrication, reducing leakage currents while maintaining capacitive coupling.

Nickel silicide for pFETs and titanium silicide for nFETs lowers contact resistance in miniaturized CMOS circuits.

A low reflection conductive line uses a composite metal and transparent oxide structure to transmit incident light through display panels.

Stacked gate bump oxide enables self-aligned N-drift and P-surf implants for optimized field shaping.

Atomic layer deposition creates tantalum silicon oxynitride high-k dielectrics, reducing equivalent oxide thickness while maintaining electrical isolation.

A semiconductor-on-insulator device uses non-oxidizing thermal treatment to diffuse germanium into silicon layers.

Segmented gate structures with localized spacer optimization resolve manufacturing complexity while enhancing device integration and charge carrier mobility.

Segmented gate insulating films improve drain current while maintaining voltage breakdown resistance in display driver ICs.

Insulating isolations within a filler cell separate adjacent standard cell active regions, resolving manufacturing precision challenges during integration.

A 3D semiconductor memory device uses stacked source layers to reduce electrical resistance in channel structures.

Varying fin depths optimizes drive current and leakage performance while avoiding photolithography depth-of-focus issues.

A thin film transistor uses segmented gate electrodes with varying widths to define a lightly doped region between channel and source-drain areas.

Forming a sacrificial spacer and air vent allows deposition of a full-thickness airgap spacer, reducing off capacitance while preserving structural integrity.

Angled ion implantation modifies oxide etch rates to control trench bottom thickness in MOSFET structures.

Segmented light shielding layers balance production times with low hydrogen layer formation, reducing contamination risks and improving stability.

Wider external wiring overlaps alternating transistor and diode portions to reduce thermal fatigue at the junction.

A semiconductor fin structure uses a one-sided constraint layer to guide asymmetric epitaxial source and drain growth.

Epitaxial growth merges fins to maximize channel strain, preventing stress relaxation in raised source and drain features.

Adjustable amplifier circuitry resolves the contradiction between measurement precision and device complexity by dynamically switching gain settings.

Reflowing an organic planarizing layer over an undercut protects the boundary between nFET and pFET regions from lateral etching of work function metal.

Segmented gate electrodes control electric fields to reduce hot electron accumulation and kink phenomenon in miniaturized transistors.