High-k Metal Gate Stack Formation for CMOS Leakage Reduction
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Solution Overview
Problem
The challenge in fabricating advanced integrated circuits is the need to maintain high capacitive coupling while avoiding short channel behavior and leakage currents, particularly with ultra-thin silicon dioxide gate insulation layers, which requires alternative high-k materials and complex integration schemes to adjust work functions and dopant profiles, but these can be compromised by high temperature treatments affecting the high-k dielectric and metal gate structures.
Innovation Solution
The formation of high-k dielectric metal gate stacks after completing transistor structures with a selective etch process, maintaining compatibility with CMOS integration schemes, and using appropriate metal-containing materials with suitable work functions for N-channel and P-channel transistors, while maintaining conventional gate electrode structures in certain areas to avoid shifts in work functions and permittivity reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If ultra-thin silicon dioxide gate insulation layers are used to maintain capacitive coupling in scaled transistors, then capacitive coupling is improved, but leakage current increases exponentially
Solution Approach 1:
The patent changes the material parameter (permittivity) by transitioning from silicon dioxide to high-k dielectric materials. This allows achieving the required capacitive coupling with a physically thicker gate insulation layer, thereby reducing tunneling leakage current while maintaining the necessary electrical capacitance for scaled transistor operation.
Solution Approach 2:
The patent employs composite gate insulation structures combining high-k dielectric materials with metal gate electrodes. This composite approach enables simultaneous optimization of capacitive coupling and leakage current reduction, as the high-k material provides enhanced capacitance while the metal gate eliminates polysilicon depletion effects that contribute to leakage.
2Reliability
If high-k dielectric metal gate stacks are formed after transistor structures, then work function shifts and permittivity reduction are avoided, but process complexity increases
Solution Approach 1:
The patent performs preliminary formation of transistor structures (channels, sources, drains) before introducing high-k dielectric metal gate stacks. This sequencing prevents high-k materials from exposing to high temperature treatments during transistor fabrication, thereby avoiding permittivity reduction and work function shifts while managing process complexity through staged manufacturing.
Solution Approach 2:
The patent segments the fabrication process into distinct stages: first forming transistor structures with conventional materials, then separately forming high-k dielectric metal gate stacks. This segmentation isolates the sensitive high-k materials from high temperature processing, preserving their electrical characteristics without requiring complete process redesign.
3Power
If different gate insulation layer thicknesses are used for N-channel and P-channel transistors, then performance optimization is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality by forming gate insulation layers with different thicknesses in different device regions. N-channel transistors receive thinner gate insulation for higher speed performance, while P-channel transistors receive thicker gate insulation for lower leakage. This spatial differentiation optimizes each transistor type's performance while managing manufacturing precision through selective processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of sophisticated transistor elements with enhanced capacitive coupling and reduced leakage currents, maintaining compatibility with conventional CMOS techniques and allowing for strain-inducing mechanisms and performance-enhancing strategies, thereby improving transistor performance and compatibility with various operating voltages.
Implementation Method 1
high-k gate dielectric of increased permittivity compared to gate dielectrics, such as silicon dioxide and silicon nitride
Implementation Method 2
the second gate electrode structure is removed on the basis of a selective etch process while the first replacement gate electrode structure remains substantially non-covered
Data Source
AI summary
In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.