Double-RESURF LDMOS Self-Aligned Implants
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Solution Overview
Problem
Conventional double-RESURF LDMOS transistors face challenges such as high on-resistance, hot carrier degradation, and difficulty in scaling for higher voltages due to complex boron implant processes and the need for multiple masks, which restricts optimization of breakdown voltage versus specific resistance characteristics.
Innovation Solution
A double-RESURF LDMOS transistor with a stacked gate dielectric structure formed using a 'bump' mask, featuring a shallow field oxide and optional raised dielectric, combined with self-aligned N-drift and P-surf implants, which reduces on-resistance and enhances the BV-to-RDSON ratio through optimal electrical field shaping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional double-RESURF LDMOS transistors use complex boron implant processes with multiple masks, then breakdown voltage can be achieved, but manufacturing complexity increases and optimization of BV-to-RDSON ratio is restricted
Solution Approach 1:
The patent extracts the boron implantation step entirely from the manufacturing process, replacing it with a simplified approach that uses only phosphorus or arsenic implants. This removes the complexity of multiple masks and sequential implantation steps while maintaining the double-RESURF functionality through alternative doping strategies.
Solution Approach 2:
The patent changes the doping parameters by substituting boron (a p-type dopant) with phosphorus or arsenic (n-type dopants). This parameter change allows achieving the same electrical field shaping and breakdown voltage characteristics through different physical mechanisms, simplifying the overall process.
2Reliability
If conventional LDMOS transistors use deep field oxide regions for isolation, then electrical isolation is achieved, but on-resistance increases due to current bypassing the field oxide
Solution Approach 1:
The patent applies local quality by creating a shallow field oxide region specifically under the gate structure rather than using deep field oxide across the entire device. This localized approach provides sufficient electrical isolation where needed while minimizing the impact on current flow paths and reducing on-resistance.
Solution Approach 2:
The patent transitions from a deep vertical field oxide structure to a shallow field oxide structure, effectively changing the dimensional approach to isolation. The isolation function is achieved through lateral field control and drift region design rather than deep vertical oxidation, reducing the harmful bypass current effect.
3Reliability
If conventional LDMOS transistors use thick field oxide regions, then hot carrier degradation is reduced, but layout area increases
Solution Approach 1:
The patent changes the field oxide thickness parameter from conventional thick values to a shallow depth, combined with modified doping profiles in the drift region. This parameter change achieves hot carrier protection through field control rather than sheer oxide thickness, reducing the required layout area.
4Manufacturing precision
If conventional double-RESURF LDMOS transistors use multiple implant masks, then precise doping profiles are achieved, but productivity decreases due to process time
Solution Approach 1:
The patent extracts the multiple mask implantation steps and replaces them with a single-implant or reduced-implant process. The precise doping profiles are achieved through optimized implant energy and dose parameters rather than sequential masked implants, significantly improving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a 20-40% improvement in the BV-to-RDSON ratio, reduces on-resistance, and maintains or improves breakdown and threshold voltages compared to conventional transistors, while simplifying the manufacturing process and minimizing layout area.
Implementation Method 1
performing a thermal oxidation process that forms a shallow field oxide ('bump oxide') on the substrate surface
Implementation Method 2
an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region are disposed below the drift (channel) region
Implementation Method 3
During operation a depletion layer extends upward from the PN junction formed by the N-drift and P-surf implants toward the portion of the polysilicon gate structure
Data Source
AI summary
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.