Dual-Gate MOSFET Well Structure for Breakdown Voltage Optimization
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Solution Overview
Problem
In semiconductor devices, particularly MOSFETs, achieving high breakdown voltage while maintaining low base resistance is challenging, leading to increased manufacturing costs and reduced drivability of parasitic bipolar transistors when high-voltage and low-breakdown voltage elements are integrated on the same substrate.
Innovation Solution
A semiconductor device structure with a dual channel (dual gate) MOSFET design, featuring a p-type well with a low impurity concentration and n-type wells with varying impurity concentrations, along with specific gate electrode lengths and overlapping configurations, is implemented to enhance breakdown voltage and reduce base resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the impurity concentration of the well or substrate is suppressed to be lower to achieve high breakdown voltage, then the breakdown voltage is improved, but the base resistance of the parasitic bipolar transistor becomes higher, reducing drivability
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the well structure. A first well region adjacent to the drain has higher impurity concentration to reduce base resistance and improve drivability, while a second well region farther from the drain maintains lower impurity concentration to preserve high breakdown voltage. This spatial differentiation of impurity concentrations allows simultaneous optimization of both contradictory requirements.
2Strength
If a high breakdown voltage structure is fabricated using additional processes against prescribed CMOS processes, then the breakdown voltage MOSFET performance is improved, but the manufacturing cost is increased
Solution Approach 1:
The patent merges the fabrication processes for high breakdown voltage MOSFETs and low breakdown voltage CMOS elements into a single integrated process flow. By designing the dual-well structure that can be formed using standard CMOS compatible steps, the invention eliminates the need for separate additional processes, thereby reducing manufacturing cost while maintaining high breakdown voltage performance.
Solution Approach 2:
The patent creates a universal well structure that serves multiple functions: it provides high breakdown voltage for MOSFET operation, maintains appropriate base resistance for parasitic bipolar transistor drivability, and is compatible with standard CMOS fabrication processes. This multi-functionality allows the same structure to satisfy multiple requirements without needing separate specialized processes.
3Reliability
If the impurity concentration is increased to reduce base resistance, then the drivability of parasitic bipolar transistor is improved, but the breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the well structure. A first well region adjacent to the drain has higher impurity concentration to reduce base resistance and improve drivability, while a second well region farther from the drain maintains lower impurity concentration to preserve high breakdown voltage. This spatial differentiation of impurity concentrations allows simultaneous optimization of both contradictory requirements.
Data Source
AI summary
An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a first conductive type on the substrate, an insulating isolation film on the substrate, a second semiconductor region with a second conductive type, the second semiconductor region being provided between the first semiconductor region and the insulating isolation film, a drain region with the second conductive type provided on a surface of the second semiconductor region, an impurity concentration of the drain region being higher than an impurity concentration of the second semiconductor region, a source region with the second conductive type provided on a surface of the first semiconductor, the source region being separated from the drain region, a floating drain region with the second conductive type provided on the surface of the first semiconductor region between the second semiconductor region and the source region, a first gate electrode above the first semiconductor region between the drain region and the floating drain region, a second gate electrode above the first semiconductor region between the source region and the floating drain region, a gate insulator provided between the first gate electrode and the surface of the first semiconductor region, the first gate electrode and the surface of the second semiconductor region, and the second gate electrode and the surface of the first semiconductor region, a portion of the second semiconductor region being placed under the first gate electrode through the gate insulator to be overlapped with the first gate electrode, a drain electrode on the drain region, and a source electrode on the source region.