Airgap Spacer Formation for Transistor Capacitance Reduction
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in reducing off capacitance due to the formation of airgap spacers after the zero via level, which reduces their efficacy and requires complex processing steps, leading to structural integrity issues with large airgaps.
Innovation Solution
The method involves forming a sacrificial spacer along the entire thickness of the gate, removing it to create an air vent passage, and depositing a second dielectric layer to form an airgap spacer that extends the full thickness of the gate sidewall, without additional spacer material, thereby maintaining the spacer's efficacy in reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If airgap spacers are formed after the zero via level, then the processing complexity is reduced, but the airgap spacer efficacy is reduced due to ILD filling
Solution Approach 1:
The airgap spacer is formed before the zero via level is created, ensuring that the spacer maintains its full efficacy in reducing capacitance. The ILD is then deposited over the airgap spacer without filling it, as the air vent passage prevents ILD intrusion into the airgap region.
2Reliability
If airgap spacers are formed before the zero via level, then the airgap spacer efficacy is maintained, but the processing complexity increases and structural integrity issues arise
Solution Approach 1:
An air vent passage is created as an intermediary structure that allows the airgap spacer to be formed before the zero via level while preventing structural integrity issues. The air vent passage acts as a mediator that enables controlled removal of sacrificial material and prevents large airgap formation issues.
Solution Approach 2:
The airgap spacer formation process is segmented into controlled steps: forming sacrificial spacers, creating air vent passages, selectively removing sacrificial material, and depositing ILD. This segmentation allows the airgap spacer to be formed effectively without requiring complex additional processing steps.
3Reliability
If large airgaps are created to reduce capacitance, then the capacitance reduction is improved, but structural integrity issues occur
Solution Approach 1:
The airgap spacer is designed with specific local characteristics: it extends along the entire thickness of the gate body sidewall but is contained within a defined region by the air vent passage. This local quality control ensures adequate capacitance reduction while maintaining structural integrity through controlled dimensions and positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance while preserving the structural integrity of the airgap spacer, avoiding the need for complex processing and maintaining the spacer's volume, thus enhancing the semiconductor device's performance.
Implementation Method 1
Reduction in off capacitance is a challenge in designing semiconductor devices. A high capacitance is attributable to the relative size of the first metal to first contact to gate body region in a field effect transistor (FET).
Implementation Method 2
removing it to create an air vent passage
Implementation Method 3
forming an airgap spacer in the at least one first dielectric layer by depositing a second dielectric layer to close off the air vent opening
Data Source
AI summary
A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.