CMOS Boundary Protection via Organic Planarizing Layer Reflow
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Solution Overview
Problem
In semiconductor fabrication, especially for multi-threshold CMOS technology, there is a challenge in accurately protecting the boundary between n-type and p-type doped field effect transistor regions during the deposition of work function metals, leading to unwanted removal of work function metal material due to edge placement inaccuracies, which affects the threshold voltage in MTCMOS devices.
Innovation Solution
A method involving the controlled reflow of an organic planarization layer is used to protect the boundary between n-type and p-type doped field effect transistor regions by creating an undercut in the organic planarizing layer, which is then refilled to prevent further lateral etching of the work function metal, allowing for complete removal without damaging the underlying metal in the other region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional boundary protection methods are used during work function metal deposition, then the boundary between nFET and pFET regions can be protected, but edge placement inaccuracies cause unwanted removal of work function metal material
Solution Approach 1:
The organic planarization layer is deposited and patterned in advance to define the boundary between nFET and pFET regions before work function metal deposition. This preliminary protective layer is then refowed to create an undercut that prevents lateral etching during subsequent metal removal processes, ensuring precise boundary protection without affecting work function metal integrity
Solution Approach 2:
The organic planarization layer undergoes a refow process where temperature and material properties are changed to create an undercut structure. This parameter change transforms the layer from a flat protective barrier to a structured feature with overhang, enabling it to prevent lateral etching of work function metal while maintaining vertical profile control
2Productivity
If work function metal is completely removed from one region, then the threshold voltage can be adjusted, but lateral etching damages the work function metal in adjacent regions
Solution Approach 1:
The organic planarization layer is selectively patterned to provide different protection levels in different regions. In the region where work function metal removal is desired, the layer is removed or thin enough to allow complete metal removal for threshold voltage adjustment. In adjacent regions, the layer remains thick and forms an undercut structure that locally prevents lateral etching, preserving work function metal integrity where needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively protects the boundary between nFET and pFET regions during work function metal removal, minimizing lateral etching and ensuring accurate threshold voltage setting in MTCMOS devices, applicable to various CMOS transistors like FinFETs and VFETs.
Implementation Method 1
reflowing includes heating the organic planarizing layer to temperature greater than a glass transition temperature of the organic planarizing layer
Implementation Method 2
decrosslinking the organic planarizing layer by exposing the organic planarizing layer to activating radiation and/or thermal radiation in an amount effective to cause the decrosslinking and reflow
Data Source
AI summary
Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.