Source-Down MOSFET Low Ohmic Current Path
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Solution Overview
Problem
The manufacturing of source-down MOSFETs with reliable insulating thermal oxides is complex and costly due to the need for higher temperatures, which poses challenges in forming sufficiently reliable electrically insulating regions on semiconductor substrates.
Innovation Solution
A method involving the formation of a semiconductor device with a deep vertical trench etched into the substrate using a dielectric region as an etch stop, accompanied by the formation of insulating layers and metallizations to create a low ohmic current path, allowing for efficient connection of control electrodes and reducing the need for high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher temperatures are used to form reliable insulating thermal oxides, then insulation reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by forming the insulating thermal oxide layer on the semiconductor substrate before subsequent processing steps. This early formation allows the oxide to serve as a stable foundation for later trench etching and metallization, avoiding the need for re-forming insulation layers after high-temperature processes, thus reducing manufacturing complexity while maintaining insulation reliability
Solution Approach 2:
The patent segments the insulation structure by creating localized insulating regions through deep vertical trenches that isolate specific areas. This segmentation allows thermal oxides to be formed only where needed, reducing the overall thermal processing burden and complexity while ensuring reliable insulation at critical interfaces between metallizations and the substrate
2Reliability
If higher temperatures are used to form reliable insulating thermal oxides, then insulation reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies local quality by concentrating thermal oxide formation and high-temperature processing only in regions where insulation is critically needed, such as at the interfaces between metallizations and the semiconductor substrate. By limiting thermal oxide formation to these localized areas rather than treating the entire substrate uniformly, the patent reduces overall manufacturing cost while maintaining insulation reliability at critical points
Solution Approach 2:
The patent performs preliminary thermal oxide formation before subsequent metallization and trench filling steps, allowing the oxide layer to be established as a cost-effective insulation foundation early in the process. This timing optimization avoids the need for expensive post-processing insulation repairs or additions, thereby reducing total manufacturing cost while ensuring reliable insulation
3Manufacturing precision
If deep vertical trenches are etched to the dielectric region using the dielectric region as an etch stop, then manufacturing precision is improved, but the etching process complexity increases
Solution Approach 1:
The patent applies self-service by designing the dielectric region to automatically function as an etch stop during trench formation. The dielectric material's inherent resistance to the etching chemistry causes the etch process to self-terminate at the dielectric-semiconductor interface, providing precise trench depth control without requiring external monitoring or control mechanisms. This self-regulating approach improves manufacturing precision while avoiding the complexity of active etch depth control systems
Solution Approach 2:
The patent uses the dielectric region as an intermediary layer that mediates between the etching process and the semiconductor substrate. This dielectric intermediary protects the substrate from direct etching while providing a well-defined termination point for the trench, ensuring precise depth control. The intermediary approach simplifies the overall etching process complexity by eliminating the need for complex multi-step etching sequences or real-time depth monitoring
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces costs, and enables reliable insulation and efficient heat dissipation in source-down MOSFETs, particularly suitable for automotive applications where additional insulation is not required.
Implementation Method 1
A deep vertical trench is etched from the main horizontal surface into the semiconductor substrate at least close to a horizontal surface of the dielectric region. The deep vertical trench can be etched to the horizontal surface of the dielectric region by using the dielectric region as an etch stop.
Implementation Method 2
On a side wall of the deep vertical trench an insulating layer is arranged.
Implementation Method 3
A low ohmic current path extends at least partially along the insulating layer and between the main horizontal surface and the back surface.
Implementation Method 4
A first metallization is formed on the main horizontal surface so that the first metallization is in ohmic contact with the first doped region.
Implementation Method 5
The control metallization is arranged on the back surface in ohmic contact with the control electrode via the low ohmic current path.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a main horizontal surface, a back surface arranged opposite the main horizontal surface, a vertical transistor structure including a doped region and a control electrode arranged next to the main horizontal surface, an insulating region arranged at or close to the back surface, a deep vertical trench extending from the main horizontal surface through the semiconductor substrate and to the insulating region, an insulating layer arranged on a side wall of the deep vertical trench, and a low ohmic current path extending at least partially along the insulating layer and between the main horizontal surface and the back surface. A first metallization is in ohmic contact with the doped region and arranged on the main horizontal surface. A control metallization is arranged on the back surface and in ohmic contact with the control electrode via the low ohmic current path.