ESD Protection Circuit Using Segmented Bipolar Transistors
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Solution Overview
Problem
High-voltage integrated circuits (ICs) face latch-up phenomena due to electrostatic discharge (ESD) when using grounded-gate LDMOS devices, which can lead to breakdown, and existing high-voltage diodes provide adequate protection but occupy large areas, making them unsuitable for ICs.
Innovation Solution
An ESD protection circuit utilizing a substrate with multiple unit bipolar transistors, each comprising specific conductivity-type wells and doping layers, connected in series to prevent latch-up and increase current efficiency per unit area, ensuring the sustaining voltage exceeds the driving voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-voltage diode is used for ESD protection, then latch-up phenomenon is avoided, but large area is occupied
Solution Approach 1:
Instead of using a single large-area high-voltage diode, the invention segments the protection function across multiple compact unit bipolar transistors connected in series. This segmentation achieves the same latch-up resistance while significantly reducing the total area occupied by the ESD protection circuit.
Solution Approach 2:
The invention optimizes the electrical parameters of unit bipolar transistors, particularly the doping concentrations and well depths, to achieve high sustaining voltage with compact device dimensions. This allows compact area while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents latch-up phenomena and enhances area efficiency by maintaining a higher sustaining voltage than the driving voltage, allowing for robust ESD protection without occupying excessive space, as demonstrated by the comparison with high-voltage diode-based circuits.
Implementation Method 1
a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well
Implementation Method 2
a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well
Data Source
AI summary
An electrostatic discharge (ESD) protection circuit includes a substrate, and a plurality of unit bipolar transistors formed in the substrate. Each of the plurality of unit bipolar transistors may include a first-conductivity-type buried layer formed in the substrate, a first-conductivity-type well formed over the first-conductivity-type buried layer, a second-conductivity-type well formed in the first-conductivity-type well, a first-conductivity-type vertical doping layer vertically formed from the surface of the substrate to the first-conductivity-type buried layer so as to surround the first-conductivity-type well, and a first-conductivity-type doping layer and a second conductivity-type doping layer formed in the second-conductivity-type well. The first-conductivity-type doping layer of any one of the adjacent unit bipolar transistors and the first-conductivity-type vertical doping layer of another one of the adjacent unit bipolar transistors may be connected to each other.