Fuse Structure for Integrated Circuit EOS Protection
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Solution Overview
Problem
Conventional semiconductor integrated circuits face challenges in protecting against electrical overstress (EOS) and electrostatic discharge (ESD) events, particularly due to the limitations of fuses and current limiting resistors in handling high current and voltage conditions, which can lead to overheating and damage, and existing high voltage protection circuits increase the size of the integrated circuit.
Innovation Solution
A fuse structure incorporating a metal fuse element connected to a stacked via fuse link and a thin film resistive element, which functions as a heating element to break the fuse circuit during EOS events, and an integrated EOS/ESD protection circuit combining a current limiting resistor with an ESD protection circuit, allowing for effective protection without consuming large silicon real estate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current limiting resistor is used for high current input-output pins instead of a fuse, then false triggering during normal operation is prevented, but the resistor consumes large silicon real estate
Solution Approach 1:
The patent merges the fuse structure with the ESD protection circuit by integrating the fuse link into the existing protection circuit layout. This combination allows the fuse to share space with other protection elements, significantly reducing the total silicon area required compared to a separate current limiting resistor approach.
Solution Approach 2:
The fuse structure is nested within the ESD protection circuit architecture, with the fuse link positioned between the I/O pad and the ESD protection circuitry. This nesting enables the fuse to be part of the protection system rather than a separate component, optimizing space utilization on the silicon die.
2Reliability
If high voltage protection circuit is used for low voltage power supply pins, then EOS protection is improved, but the circuit size increases
Solution Approach 1:
The patent applies local quality by creating a localized fuse link with specific geometric properties (narrower width, reduced cross-sectional area) at a precise location within the circuit. This localized modification provides high voltage/EOS protection without requiring a full high voltage protection circuit, thereby maintaining compact overall circuit size.
Solution Approach 2:
The fuse link acts as an intermediary protective element between the low voltage power supply pin and the rest of the circuit. It provides EOS protection by breaking under excessive voltage/current conditions without requiring the complex architecture of a complete high voltage protection circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively prevents overheating and damage from EOS events while allowing normal operation during ESD events, and provides compact EOS and ESD protection for both high and low voltage pins, reducing the risk of false triggering and size constraints.
Implementation Method 1
A fuse structure incorporates a metal fuse element connected to a stacked via fuse link and a thin film resistive element, which functions as a heating element to break the fuse circuit during EOS events
Data Source
AI summary
In some embodiment, a fuse structure in a semiconductor device uses a metal fuse element connected to a stacked via fuse link connected to a thin film resistive element. The fuse structure can be incorporated in an integrated circuit for EOS protection. In other embodiments, an integrated EOS/ESD protection circuit includes a current limiting resistor integrated with an ESD protection circuit. In some embodiments, the current limiting resistor is formed in an N-well forming the collector of the ESD protection circuit.