Metallic Local Interconnect Resistors for Semiconductor ICs
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Solution Overview
Problem
In semiconductor integrated circuit manufacturing, polysilicon and active region features are more vulnerable to process variations than metallic features, leading to larger minimum sizes for achieving predetermined resistance values, resulting in increased area occupation and manufacturing complexity.
Innovation Solution
The use of conductive structures in the local interconnection layer with a resistance value greater than 50 ohms, formed using metallic materials like tungsten or aluminum, which are compatible with silicon or silicon germanium, allowing for smaller feature sizes and reduced area occupation compared to polysilicon or active region resistors without additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polysilicon or active region features are used to form resistors, then the resistance value can be achieved, but the feature size must be larger due to vulnerability to process variations
Solution Approach 1:
The patent changes the material parameter from polysilicon to metallic materials (tungsten, aluminum, copper), which fundamentally alters the resistance characteristics and allows for smaller feature sizes while maintaining process variation tolerance. This material substitution enables achieving the same resistance value with significantly reduced area.
Solution Approach 2:
The patent uses standard metallic interconnection layer materials that are already part of the CMOS fabrication process, rather than requiring specialized polysilicon resistor materials. These metallic materials are formed using existing deposition and etching tools, making the process more economical and compatible with standard manufacturing flows.
2Manufacturing precision
If polysilicon or active region resistors are used, then resistance values can be formed, but the manufacturing process becomes more complex
Solution Approach 1:
The patent makes the metallic conductive structures serve dual functions: as interconnection elements and as resistors. By forming resistors from the same metallic materials and process steps used for interconnects, the invention eliminates the need for separate polysilicon resistor formation processes, reducing overall manufacturing complexity.
Solution Approach 2:
The patent merges the resistor formation process with the standard metallic interconnection layer formation process. Both interconnects and resistors are formed simultaneously using the same deposition, patterning, and etching steps, eliminating redundant process steps and simplifying the overall fabrication flow.
3Reliability
If larger feature sizes are used for polysilicon resistors, then process variation tolerance is achieved, but the chip area occupation increases
Solution Approach 1:
The patent changes the material parameter from polysilicon to metals with inherently lower sensitivity to process variations. Metallic materials like tungsten and aluminum have more stable resistance characteristics that are less affected by dimensional variations, allowing smaller features to achieve the same reliability.
Solution Approach 2:
The patent replaces the mechanical/dimensional approach (larger polysilicon features) with a material-based approach (metallic materials with favorable electrical properties). This substitution allows achieving process variation tolerance through material selection rather than increased dimensions.
Data Source
AI summary
The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.