Tuneable Diffusion Resistor for CMOS Process Variation
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Solution Overview
Problem
Current semiconductor resistors lack adjustable resistance that can be controlled by users, leading to variations due to process and mismatch issues, requiring design guard-banding and increased manufacturing time.
Innovation Solution
An on-chip tuneable diffusion resistor is developed, comprising a metal or polysilicon layer on an insulating layer with a diffusion well in the silicon substrate, where two implant regions define terminals and a voltage difference is applied to establish a depletion region, reducing the effective thickness and increasing resistance, allowing for adjustable resistance during circuit operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fixed resistors are used in silicon technologies, then manufacturing process is simple, but resistance value cannot be adjusted and suffers from process and mismatch variation
Solution Approach 1:
The patent transforms a static resistor into a dynamic, tuneable component by applying reverse bias voltage to the diffusion well. The depletion region width varies with applied voltage, dynamically changing the effective resistance value. This allows the resistor to adapt its resistance to minimize mismatch and process variation effects in circuits like current mirrors and ADCs.
Solution Approach 2:
The patent changes the electrical parameters of the diffusion well by applying reverse bias voltage. The depletion region depth and width are modified through voltage control, which directly alters the resistance value. This parameter change enables the resistor to compensate for process variations and mismatch without requiring additional manufacturing precision.
2Reliability
If design guard-banding is used to account for resistance variations, then reliability is improved, but design flexibility is reduced and manufacturing time increases
Solution Approach 1:
The tuneable resistor provides self-adjustment capability through voltage control. The resistance automatically adapts to minimize mismatch and process variation effects, eliminating the need for external trimming or complex design guard-banding. This self-service mechanism reduces both design complexity and manufacturing time while maintaining reliability.
3Manufacturing precision
If trim bias and testing are performed during manufacturing, then resistance precision is improved, but productivity is reduced
Solution Approach 1:
The patent performs preliminary resistance tuning during the manufacturing process by applying reverse bias voltage to establish the desired resistance value before final circuit operation. This preliminary action sets the resistor characteristics in advance, eliminating the need for subsequent trimming or testing steps, thereby improving productivity without sacrificing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution minimizes mismatch and process variation in circuits like current mirrors and ADCs, reduces manufacturing time, and eliminates the need for trim bias, while being constructed with existing semiconductor layers, enabling precise resistance control with less precision required for gate voltage adjustment.
Implementation Method 1
A depletion region is established beneath the insulating layer, by the voltage applied to the conduction layer above the insulator, and the effective thickness of the resistor is reduced. With the effective thickness of the resistor reduced, the resistance is increased.
Data Source
AI summary
An object of the disclosure is to take a CMOS varactor structure (NMOS in N-well or PMOS in P-well) and turn it in to a three terminal on-chip tuneable diffusion resistor. The diffusion resistor can be made with an n+ diffusion inside the p-substrate, or with a p+ diffusion inside an N-well that lies within the p-substrate. The resistor can be implemented in any existing CMOS or BICMOS silicon technology, without using additional masks. The resistor can be also implemented in a technology with FINFETs.