Memory Structure With Tip Erase Reducing Voltage
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Solution Overview
Problem
Current non-volatile memory devices face challenges in improving electrical performance, particularly in erase operations and write reliability, due to limitations in voltage requirements and programming paths.
Innovation Solution
A memory structure with a charge storage layer having a recess and a tip, where the erase operation can be performed through tip erase, reducing erase voltage and allowing programming and erase operations to be conducted through different paths, enhancing the electrical performance by using a substrate with a memory cell region and a peripheral circuit region, and employing dielectric and conductor layers with specific configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory structure is used, then manufacturing process is simple, but erase voltage is high and electrical performance is limited
Solution Approach 1:
The charge storage layer is segmented into multiple parts: a main body portion and a tip portion extending from it. The tip portion is positioned adjacent to the gate electrode, creating distinct functional zones that enable separate programming and erase operations through different physical paths, thereby improving electrical performance without requiring complete structural redesign
Solution Approach 2:
The charge storage layer transitions from a planar two-dimensional structure to a three-dimensional structure with a tip portion extending vertically or laterally. This dimensional change creates additional spatial pathways for charge injection and removal, enabling independent programming and erase operations that improve electrical performance while maintaining manufacturing feasibility
2Power
If tip erase is implemented, then erase voltage is reduced, but charge storage layer structure becomes more complex
Solution Approach 1:
The charge storage layer exhibits local quality variations with a tip portion having different geometric characteristics than the main body. The tip portion is specifically positioned and dimensioned to enable localized electric field enhancement during erase operations, allowing reduced erase voltage while maintaining overall structural simplicity through targeted local modifications rather than complete redesign
3Reliability
If programming and erase operations use different paths, then write reliability is enhanced, but device structure becomes more complex
Solution Approach 1:
The charge storage layer is divided into functionally distinct regions: a main body portion for charge storage and a tip portion for erase operations. This segmentation enables programming electrons to be injected into the main body through one path while erase operations remove electrons from the tip portion through a different path, enhancing write reliability by preventing interference between programming and erase mechanisms
Data Source
AI summary
A memory structure including a substrate, a charge storage layer, a first gate, a first dielectric layer, and a second dielectric layer is provided. The substrate includes a memory cell region. The charge storage layer is located on the substrate in the memory cell region. The charge storage layer has a recess. The charge storage layer has a tip around the recess. The first gate is located on the charge storage layer. The first dielectric layer is located between the charge storage layer and the substrate. The second dielectric layer is located between the first gate and the charge storage layer.