Non-Planar Transistor for Embedded DRAM Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current technologies face challenges in scaling down computer memory beyond 22 nm nodes while maintaining low leakage and improved retention time, particularly in integrating DRAM with conventional planar SOI CMOS devices.
Innovation Solution
The method involves forming a memory cell with a trench capacitor and a non-planar transistor, such as a finFET, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor, all within a monolithic silicon substrate, enabling continued device scaling and improved electrostatic shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional planar SOI CMOS devices are used, then manufacturing compatibility is maintained, but device scaling beyond 22 nm nodes cannot be achieved
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional multigate structures (FinFET, trigate, nanowire) that wrap around the channel in multiple directions. This dimensional change enables continued scaling beyond 22 nm by providing superior electrostatic control over the channel through gates that contact the channel from top, bottom, and sidewalls, effectively solving the scaling limitation of conventional planar devices.
Solution Approach 2:
The patent implements nested gate structures where multiple gate electrodes are positioned at different levels and orientations around a central channel region. The gates are nested concentrically or in layered configurations, with inner gates closer to the channel center and outer gates providing additional control, creating a multi-layered electrostatic shielding system that maintains control as device dimensions shrink.
2Quantity of substance
If device scaling is pursued to increase density, then memory density improves, but leakage increases and retention time decreases
Solution Approach 1:
By moving to three-dimensional multigate structures where gates wrap around the channel from multiple directions (top, bottom, sidewalls), the patent achieves superior electrostatic control that suppresses short-channel effects and leakage currents. This multi-directional gating provides enhanced electrostatic shielding that maintains low leakage and improved retention time even as device dimensions scale down to increase density.
Solution Approach 2:
The patent employs composite transistor structures combining multiple gate materials with different work functions, dielectric materials with varying permittivities, and channel materials optimized for specific performance characteristics. This composite approach allows tuning of electrostatic control and leakage characteristics to achieve both high density and low leakage/long retention performance simultaneously.
3Reliability
If multigate devices are implemented, then electrostatic shielding and retention time improve, but integration with conventional planar CMOS becomes difficult
Solution Approach 1:
The patent segments the transistor fabrication process into distinct modules: forming the channel structure (fin, wire, or nanowire), depositing gate materials, creating isolation structures, and forming contacts. Each module can be independently optimized and integrated with conventional CMOS process steps, allowing multigate devices to be incorporated into existing manufacturing lines with minimal disruption to overall process compatibility.
Solution Approach 2:
The patent develops universal process modules and material systems for multigate device fabrication that can be applied across different device types (FinFET, trigate, nanowire) and integrated with both n-type and p-type CMOS devices. The same fundamental process techniques and material choices serve multiple functions and device configurations, simplifying integration with conventional planar CMOS technologies.
Data Source
AI summary
A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.