Dielectric Fuse Memory Circuit for Low Power Data Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing one-time programming (OTP) memory technologies face challenges with high operating current, large area requirements, small read margin, charge loss, and poor data retention, particularly in anti-fuse type memories, which limit their suitability for complex data storage applications.
Innovation Solution
The integrated circuit memory design incorporates two field-effect transistors connected in series, utilizing a dielectric fuse mechanism where an electric signal changes the conductivity of the gate dielectric layer from high to low state for storage, allowing for stable conductivity states and efficient information storage with low operating current and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fuse-type wire memory is used, then data storage is achieved through metal atomic movement, but large area and high operation current are required
Solution Approach 1:
The patent changes the fundamental storage mechanism from metal atomic movement (fuse-type) to dielectric conductivity change (anti-fuse type). By applying high voltage to induce dielectric breakdown, the gate dielectric transitions from high resistance to low resistance state, achieving data storage with smaller area and lower current requirements.
Solution Approach 2:
The patent replaces the mechanical metal atomic movement process with an electrical dielectric breakdown process. Instead of physically moving metal atoms through electromigration, the invention uses electrical field-induced dielectric breakdown to change conductivity states, eliminating the need for large-area metal interconnect structures.
2Area of stationary object
If anti-fuse type memory is used, then area per unit cell is reduced and operation current is lowered, but charge loss occurs and data retention is poor
Solution Approach 1:
The patent implements a dual-transistor structure where one transistor serves as a control device and the other as a storage device with dielectric breakdown. This configuration provides stable read/write operations and prevents charge loss by using the control transistor to manage the storage transistor's state, thereby cushioning against retention issues.
Solution Approach 2:
The patent uses a composite structure combining two different transistor types with distinct functions. The control transistor maintains stable electrical characteristics while the storage transistor utilizes dielectric breakdown for data retention, creating a composite system that overcomes the limitations of single-transistor anti-fuse memory.
3Reliability
If gate dielectric thickness is reduced to achieve anti-fuse breakdown, then breakdown electric field decreases and conductivity changes from low to high, but operation margin becomes small
Solution Approach 1:
The patent segments the memory cell into two distinct transistors: a control transistor for stable operation and a storage transistor for dielectric breakdown. This segmentation allows the control transistor to provide a stable reference state while the storage transistor undergoes controlled breakdown, thereby maintaining adequate read margin despite thin gate dielectric.
Solution Approach 2:
The control transistor acts as an intermediary between the input signal and the storage dielectric. It regulates the voltage applied to the storage transistor, enabling controlled dielectric breakdown while maintaining stable read operations. This intermediary function prevents direct exposure of the thin dielectric to full voltage swings, preserving read margin.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves stable read/write operations with low power consumption, improved data retention, and reduced noise, outperforming traditional fuse-type wire and anti-fuse type memories in terms of area efficiency and operational margin.
Implementation Method 1
as the thickness of the gate dielectric layer is getting thinner, the breakdown electric field of the dielectric layer becomes lower; and therefore, such breakdown causes the changes of gate dielectric conductivity from low to high so as to form anti-fused type
Data Source
AI summary
One time programming and repeatably random read integrated circuit memory has a storage device that programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.