Asymmetrical FinFET Source/Drain for Parasitic Capacitance
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Solution Overview
Problem
Conventional FinFETs with symmetrically extended source/drain features experience undesirable parasitic capacitance issues due to proximity of neighboring transistors, particularly in advanced technology nodes, where the increased density of transistors on a single chip leads to significant parasitic capacitance values.
Innovation Solution
The implementation of an asymmetrical source/drain feature in FinFETs, where a constraint structure is formed on one side to restrict growth towards that side and allow greater extension towards the opposite side, where components are more sparse, thereby controlling the growth and reducing parasitic capacitance by forming an asymmetrical profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If symmetrically extended source/drain features are used in conventional FinFETs, then manufacturing simplicity is maintained, but parasitic capacitance increases due to proximity of neighboring transistors
Solution Approach 1:
The patent applies asymmetry by forming constraint structures (mandrels) on only one side of the fin channel, causing the source/drain feature to extend asymmetrically. This asymmetric extension reduces parasitic capacitance between neighboring transistors while maintaining manufacturing simplicity through a single-sided constraint structure formation process
2Productivity
If transistor density is increased on a single chip to meet technology node evolution, then productivity is improved, but parasitic capacitance between neighboring FinFETs becomes intolerable
Solution Approach 1:
The asymmetric source/drain extension allows transistors to be placed closer together while maintaining acceptable parasitic capacitance levels. The constraint structure on one side creates an asymmetric profile that reduces the capacitive coupling between adjacent devices, enabling higher transistor density without intolerable parasitic effects
3Shape
If source/drain features are allowed to extend equally in both directions, then structural symmetry is maintained, but parasitic capacitance between adjacent source/drain features increases
Solution Approach 1:
The patent deliberately breaks structural symmetry by forming constraint structures on only one side of the fin channel. This asymmetric configuration causes the source/drain feature to extend further on the unconstrained side, thereby reducing the distance and parasitic capacitance between adjacent source/drain features of neighboring transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between neighboring FinFETs by guiding the asymmetrical source/drain growth, enhancing the performance and reducing issues such as short circuits and parasitic capacitance, especially in densely packed transistor configurations.
Implementation Method 1
The asymmetrical source/drain feature is guided to grow towards a first side based on a constraint structure
Data Source
AI summary
A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.