3D Nonvolatile Memory Source Resistance Reduction
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Solution Overview
Problem
The driving speed of three-dimensional (3-D) nonvolatile memory devices is limited by the high resistance of the source region, which is formed by doping an N-type impurity into the substrate.
Innovation Solution
The introduction of channel layers protruded from a substrate with word line structures that include word lines stacked over the substrate, first and second junctions formed in the substrate between adjacent word line structures, source lines coupled to the first junctions, and well pickup lines coupled to the second junctions, along with subgate lines to control channel formation and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the source region is formed by doping an N-type impurity into the substrate, then the memory device structure is simple, but the resistance of the source region is high which limits driving speed
Solution Approach 1:
The substrate is divided into multiple regions with different doping types (first doped region with N-type impurity, second doped region with P-type impurity) to create distinct functional zones. This segmentation allows the source region to be formed with lower resistance by utilizing the P-type doped region instead of relying solely on N-type doping, thereby improving driving speed while maintaining structural simplicity
Solution Approach 2:
Different regions of the substrate are assigned different doping characteristics (N-type in first doped region, P-type in second doped region) to optimize local electrical properties. The source region specifically utilizes the P-type doped region to achieve lower resistance, while other regions maintain their designated doping types for their respective functions, thus improving driving speed without compromising overall device functionality
2Quantity of substance
If channel layers are protruded from the substrate with word line structures stacked over, then memory cell density is improved, but threshold voltage regularity becomes irregular
Solution Approach 1:
Subgate lines are selectively applied to specific regions between adjacent word line structures to locally control channel formation. This localized control mechanism ensures that threshold voltages remain regular across different memory cells by compensating for variations in channel properties, while still allowing high memory cell density through the protruded channel layer structure
Solution Approach 2:
The subgate lines provide a feedback mechanism to regulate and equalize threshold voltages across memory cells. By monitoring and adjusting channel formation through subgate control, the system compensates for manufacturing variations and maintains threshold voltage regularity even as memory cell density increases with protruded channel layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the resistance of the source region, thereby improving the driving speed and regularizing threshold voltages of memory cells, enhancing the overall performance of the memory device.
Implementation Method 1
first junctions and second junctions formed in the substrate between the word line structures adjacent to each other
Data Source
AI summary
A three-dimensional (3-D) nonvolatile memory device includes channel layers protruded from a substrate, word line structures configured to include word lines stacked over the substrate, first junctions and second junctions formed in the substrate between the word line structures adjacent to each other, source lines coupled to the first junctions, respectively, and well pickup lines coupled to the second junctions, respectively.