3D Memory Interconnect Layout for Stronger Spacer Regions
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Solution Overview
Problem
The scaling of planar NAND memory cells is reaching its limits, leading to challenges in memory density and fabrication costs, while 3D NAND memory architecture offers a solution but faces issues with uneven topography and reduced device strength due to spacer regions in semiconductor structures.
Innovation Solution
A novel 3D memory device design with staggered dummy interconnection structures in spacer regions and a parallel fabrication process for semiconductor structures, enhancing memory density and device strength by reducing chip size and improving electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar NAND memory cells are scaled to smaller sizes, then memory density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar 2D memory architecture to 3D vertical memory architecture. Memory stacks are formed vertically extending from the substrate, with channel structures running through the stacks in the vertical direction. This dimensional change allows continued scaling and density improvement without the fabrication complexity constraints that limit planar scaling.
2Quantity of substance
If 3D NAND memory architecture is implemented, then memory density is improved, but device strength is reduced due to spacer regions
Solution Approach 1:
The patent introduces dummy interconnection structures that replicate the geometry and electrical properties of functional interconnection structures. These dummy structures are positioned in spacer regions to provide mechanical support and maintain structural integrity without interfering with memory operations. By copying the interconnection design, the patent strengthens the device in spacer regions while preserving the 3D architecture's density advantages.
3Quantity of substance
If spacer regions are included in 3D memory structure, then memory density is improved, but topography uniformity deteriorates
Solution Approach 1:
The patent applies different structures to different regions: functional memory stacks in active regions and dummy interconnection structures in spacer regions. The dummy structures match the height and geometry of functional interconnections, creating local uniformity in spacer regions that contributes to overall topography uniformity across the device surface.
Solution Approach 2:
The patent modifies the interconnection structure parameters (height, width, material composition) in spacer regions to match those in active memory regions. By changing the parameters of dummy interconnection structures to mirror functional ones, the patent achieves uniform topography across the entire device, enabling consistent subsequent processing steps.
4Quantity of substance
If chip size is reduced to increase memory density, then memory density is improved, but I/O throughput may be affected
Solution Approach 1:
The patent utilizes vertical interconnection through stacked architectures and through-silicon vias to maintain I/O throughput despite reduced chip footprint. Data and control signals are transmitted vertically through multiple memory stack layers, enabling high-speed I/O operations from a compact planar area.
Solution Approach 2:
The patent combines multiple interconnection functions into integrated vertical pathways that simultaneously handle data, address, and control signals. By merging signal routes and using shared vertical interconnection structures, the patent maintains high I/O throughput while minimizing the chip area required for interconnection infrastructure.
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device can comprise a plurality of memory regions each comprising a memory stack and a plurality of channel structures vertically extending through the memory stack, a spacer region between the plurality of memory regions, comprising a dielectric stack located between adjacent memory stacks, and a patterned conductive layer on the memory stacks and the dielectric stack. The patterned conductive layer comprises interconnection structures in the memory regions and coupled with the plurality of channel structures, and dummy interconnection structures on the dielectric stack in the spacer region and arranged in a staggered manner.