3D Memory Isolation Structure for Source Select Gate Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 3D memory devices, the etch loading effect and growth failure or defects in semiconductor plugs can lead to short-circuits between the source select gate (SSG) and the substrate, causing leakage current and device failure, especially in edge regions where channel holes are prone to unsatisfied etching and polymer residual issues.
Innovation Solution
The implementation of isolation structures surrounding channel structures in the edge region during the fabrication process, which separates the SSG sacrificial layer from the channel holes, preventing short-circuits by maintaining a lateral distance between the SSG and the semiconductor plugs, even if growth failures or voids occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If channel holes are formed in edge regions during fabrication, then memory array coverage is improved, but etch loading effect and polymer residual cause unsatisfied etching and growth failure in semiconductor plugs
Solution Approach 1:
The patent introduces an isolation structure as an intermediary element positioned between the SSG sacrificial layer and channel holes in edge regions. This isolation structure prevents direct interaction between the two, eliminating the harmful etch loading effect and polymer residual accumulation that occur when channel holes are formed adjacent to the SSG sacrificial layer. The intermediary structure enables successful etching and semiconductor plug growth in edge regions without compromising manufacturing precision.
2Ease of manufacture
If channel holes are formed close to SSG sacrificial layer, then fabrication process is simplified, but short-circuits occur between SSG and substrate due to growth failure or voids in semiconductor plugs
Solution Approach 1:
The isolation structure serves as a protective intermediary that physically separates the SSG sacrificial layer from channel holes in edge regions. This prevents short-circuits between the SSG and substrate by ensuring that even if semiconductor plugs experience growth failure or form voids, the isolation structure maintains the necessary lateral distance to prevent electrical leakage. The structure preserves fabrication simplicity while significantly improving device reliability.
Solution Approach 2:
The isolation structure provides beforehand cushioning by pre-establishing a protective barrier before semiconductor plug formation. This anticipatory measure ensures that potential growth failures or voids in semiconductor plugs will not lead to short-circuits, as the isolation structure has already positioned a lateral distance barrier between the SSG sacrificial layer and channel holes, cushioning against future defects.
3Reliability
If isolation structures are added to separate SSG from channel structures, then SSG leakage is prevented, but fabrication process complexity increases
Solution Approach 1:
The patent merges the formation of the isolation structure with existing fabrication processes. The isolation structure is formed using the same dielectric material layers that are already part of the memory stack fabrication sequence, and the patterning is integrated with the existing lithography and etching steps. This merging approach prevents SSG leakage while minimizing the increase in fabrication process complexity, as the isolation structure utilizes existing process capabilities rather than requiring entirely new process steps.
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, and one or more isolation structures. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). Each isolation structure surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure.