Digital Storage TRIZ Cases
- Bottom-Pinned SOT-MRAM Injection Layout to Prevent Current Bypass
Splitting the injection layer and adding a blocking section forces current through the SOT layer, cutting write current and transistor width.
- 3D Cross-Point Memory Array Fabrication With Via-Patterned Deck Stacking
Via-patterned composite stacks enable concurrent multi-deck cross-point memory fabrication, raising 3D density while cutting process steps and cost.
- Magnetic Tunneling Junction Oxide Stack for Stable PMA and Fast Switching
Using a higher-oxygen-affinity oxide cap limits oxygen interdiffusion, stabilizes PMA, and supports sub-10 ns MTJ switching.
- Stacked Oxide Memory Cell Structure for Higher Storage Density
A vertically stacked oxide memory cell uses low-resistance regions and shared lines to raise storage density without sacrificing productivity.
- Vertical Memory Cell Layout With Air Gaps for Noise Isolation
Air gaps and shielding structures between word lines and active patterns cut coupling noise and leakage while preserving dense vertical memory layouts.
- Gated Ferroelectric Memory Cells With Vertical Selector Switching
A vertical field-controlled selector in BEOL ferroelectric memory cells cuts footprint while preserving gate control and nonvolatile storage.