Dual-Path Latch Control for Glitch-Free Storage Reads
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Solution Overview
Problem
Leakage currents in storage circuits cause incorrect read values due to improper timing of latch control signals, leading to Q glitches and power inefficiencies.
Innovation Solution
Implement a latch control circuit with dual signal propagation paths, delaying the latch enable signal by Δt when the keeper circuit is enabled to synchronize it with the global data line signal, reducing Q glitches and false transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the latch control signal is provided through a single propagation path, then the circuit complexity is low, but the timing accuracy is insufficient causing Q glitches and false transitions
Solution Approach 1:
The latch control circuit is divided into multiple signal propagation paths (first path and second path) with different delay characteristics. Each path processes the latch control signal differently, allowing precise control over the timing of the latch enable signal to eliminate Q glitches and false transitions.
Solution Approach 2:
The circuit dynamically selects between different signal propagation paths based on the state of the keeper circuit. When the keeper circuit is enabled, the second path with additional delay is selected; when disabled, the first path is used. This dynamic adaptation optimizes timing accuracy for different operating conditions.
2Reliability
If the latch enable signal is delayed to synchronize with the global data line, then false transitions are reduced, but the propagation time increases
Solution Approach 1:
An intermediate delay mechanism is introduced in the second signal propagation path, controlled by the keeper circuit state. This intermediary delay element (such as an additional inverter or delay buffer) precisely adjusts the timing of the latch enable signal to match the global data line arrival time, eliminating false transitions without excessive delay.
3Reliability
If timing synchronization is achieved using additional delay circuits, then Q glitches are minimized, but the power consumption increases
Solution Approach 1:
The circuit dynamically activates delay elements only when necessary, based on the keeper circuit state. The second propagation path with additional delay components is enabled only when the keeper circuit is active, allowing timing synchronization to be achieved with minimal power consumption during normal operation.
Data Source
AI summary
A storage system and circuits therefor. A storage system includes a bitcell array comprising a plurality of storage cells arranged in one or more columns and one or more rows; a latch circuit configured to output a latch signal responsive to a latch control signal and a data signal from a global data line during a read operation of a storage cell of the plurality of storage cells; a latch control circuit configured to provide the latch control signal to the latch circuit, where the latch control circuit comprises a first signal propagation path for a first mode of operation and a second signal propagation path for a second mode of operation, and wherein the first signal propagation path is to delay propagation of a pulse signal through the first signal propagation path by a time (Δt) compared to a propagation of the pulse signal through the second propagation path.