Capacitive Inverter Delay Circuit for Long Timing at Minimum Gate Length
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Solution Overview
Problem
In semiconductor devices, achieving a long delay time while maintaining uniform transistor characteristics is challenging due to the difficulty in controlling the pitch of polymers as gate lengths approach the minimum feature size, leading to variations in transistor characteristics.
Innovation Solution
A delay circuit design that includes an inverter circuit unit with capacitors providing loading capacitance and resistance units, allowing for increased delay time without altering the gate length, thereby maintaining uniform transistor characteristics and minimizing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the gate length is increased to increase delay time, then the delay time is improved, but the uniformity of transistor characteristics deteriorates due to difficulty in controlling polymer pitch
Solution Approach 1:
The delay circuit is divided into multiple inverter stages (first inverter, second inverter, third inverter) connected in series. Each inverter stage has a gate length equal to the minimum feature size, but the cumulative delay across multiple stages achieves the required long delay time without requiring any single transistor to have a non-minimum gate length, thus maintaining manufacturing precision.
2Duration of action of moving object
If multiple inverter stages are used to increase delay time while keeping gate length at minimum feature size, then the delay time is improved, but the circuit area increases
Solution Approach 1:
Capacitor units are merged with the inverter circuit structure. The capacitor units are electrically connected to the inverters and provide loading capacitance to increase delay time. By integrating the capacitors into the inverter stages rather than adding separate delay elements, the circuit achieves long delay time with minimal additional area.
3Manufacturing precision
If the gate length is at minimum feature size, then the manufacturing precision is improved, but the delay time is minimized
Solution Approach 1:
Capacitor units are preliminarily connected to the inverter circuit to provide loading capacitance. This preliminary addition of capacitance loading creates a deliberate delay in the signal propagation through the inverters, allowing the circuit to achieve long delay time while maintaining minimum feature size gates for manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases delay time while maintaining uniform transistor characteristics, achieving a long delay time with minimal area and power consumption, thus addressing the challenge of varying transistor characteristics at minimum feature sizes.
Implementation Method 1
at least one capacitor unit connected to the at least one inverter, the at least one capacitor unit providing a loading capacitance to the inverter circuit unit
Data Source
AI summary
A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased.