Vertical Memory Cell Layout With Air Gaps for Noise Isolation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in maintaining production yield and integration density as design rules decrease, particularly with vertical channel transistors, which require innovative solutions to enhance electric characteristics and reduce coupling noise.
Innovation Solution
The semiconductor memory device incorporates a design with alternating first and second active patterns, including horizontal and vertical portions, and word lines, along with insulating patterns to create air gaps or shielding structures between adjacent elements, which reduces coupling noise and prevents leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If design rule is decreased to increase integration density, then integration density increases, but coupling noise between adjacent elements increases
Solution Approach 1:
An intermediate structure is introduced between adjacent word lines and between active patterns to act as a shielding barrier. This intermediate structure reduces coupling noise between adjacent elements while maintaining compact layout for high integration density.
Solution Approach 2:
The device structure is segmented into alternating first and second active patterns with corresponding word lines, creating distinct regions separated by intermediate structures. This segmentation allows independent optimization of each region while reducing mutual interference through the intermediate shielding elements.
2Area of moving object
If vertical channel transistors are used to increase integration density, then integration density increases, but leakage currents between adjacent structures increase
Solution Approach 1:
The intermediate structure serves as an electrical isolation barrier between adjacent vertical channel transistors and active patterns. This shielding structure prevents leakage currents from flowing between adjacent structures while maintaining the vertical channel configuration for high integration density.
3Object-affected harmful factors
If alternating first and second active patterns with horizontal and vertical portions are used, then coupling noise is reduced, but device structure complexity increases
Solution Approach 1:
The device employs asymmetric alternating patterns of first and second active patterns with different orientations (horizontal and vertical portions). This asymmetric design creates natural shielding effects that reduce coupling noise while the regular alternating pattern maintains manufacturing feasibility.
Data Source
AI summary
A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.