Ferroelectric Bitcell Level Conversion for Zero-Leakage State Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The integration of non-volatile logic (NVL) elements, specifically using ferroelectric capacitors in a system on chip (SoC), allows for complete power removal without losing state information, enabling instant-on capabilities and reducing energy consumption by storing state in NVL arrays that can restore system state quickly upon power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and additional power supply circuitry is required
Solution Approach 1:
The patent changes the fundamental parameter of state retention from volatile (requiring continuous power) to non-volatile (retaining state without power). By using ferroelectric capacitors with hysteresis characteristics, the system achieves zero leakage current in standby mode while maintaining data retention through the remnant polarization of the ferroelectric material.
Solution Approach 2:
The patent extracts the power consumption function from the state retention mechanism. Instead of using powered shadow latches that require continuous supply voltage, the invention uses non-volatile ferroelectric bitcells that retain state information without any power, completely removing the leakage current problem associated with traditional retention circuits.
2Loss of energy
If non-volatile logic elements are used to eliminate leakage current, then energy consumption is reduced, but signal level conversion between different voltage domains is required
Solution Approach 1:
The patent makes the sense amplifier multi-functional by having it perform both its traditional read function and an additional signal level conversion function. The sense amp converts the high-voltage ferroelectric signal to the low-voltage logic domain, eliminating the need for separate level conversion circuitry and reducing overall device complexity.
Solution Approach 2:
The patent merges the signal level conversion function with the existing sense amplifier circuit. By combining these two functions into a single circuit element, the invention avoids adding separate level conversion circuitry, thereby maintaining simplicity while achieving voltage domain compatibility between the non-volatile memory and volatile logic.
3Loss of energy
If ferroelectric capacitors are used in non-volatile bitcell array, then zero leakage in sleep mode is achieved, but voltage level mismatch between core logic and memory array must be handled
Solution Approach 1:
The patent segments the system into distinct voltage domains: a high-voltage domain for the ferroelectric memory array and a low-voltage domain for the core logic. This segmentation allows each domain to operate at its optimal voltage level while the sense amplifier acts as an interface between the domains, managing voltage level transitions without affecting the zero-leakage property of the memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables zero leakage in sleep mode and rapid system state restoration, optimizing energy usage and eliminating the need for continuous power to retain flip-flop states, making it suitable for energy-harvesting applications and handheld devices with limited power resources.
Implementation Method 1
a sense amp coupled to node Q of the selected bit cell...senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage
Implementation Method 2
Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q
Data Source
AI summary
A system on chip (SoC) includes one or more core logic blocks that are configured to operate on a lower supply voltage and a memory array configured to operate on a higher supply voltage. Each bitcell in the memory has two ferroelectric capacitors connected in series between a first plate line and a second plate line to form a node Q. A data bit voltage is transferred to the node Q by activating a write driver to provide the data bit voltage responsive to the lower supply voltage. The data bit voltage is boosted on the node Q by activating a sense amp coupled to node Q of the selected bit cell, such that the sense amp senses the data bit voltage on the node Q and in response increases the data bit voltage on the node Q to the higher supply voltage.