Mixed-Voltage I/O Circuit Biasing for Leakage-Safe Level Shifting
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Solution Overview
Problem
Conventional mixed-voltage I/O interfaces in CMOS technology face issues with leakage current, gate oxide reliability, and hot-carrier injection, particularly under low voltage operating conditions, leading to decreased performance and reliability.
Innovation Solution
An input/output (I/O) circuit design that includes a pull-up and pull-down transistor configuration with a level shifter and signal control circuit to manage voltage levels, applying high and intermediate voltages to prevent leakage current and hot-carrier injection, while maintaining gate oxide reliability across varying voltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pull-up PMOS transistor is used in a mixed-voltage I/O interface, then the I/O interface can support higher voltage external signals, but unwanted leakage current occurs from the I/O pad to the power supply
Solution Approach 1:
An intermediate voltage node is introduced between the I/O pad and the pull-up PMOS transistor. This intermediate node acts as a mediator that allows the pull-up transistor to be controlled at a lower voltage level while still being able to drive the higher voltage I/O pad, thereby preventing the direct leakage current path while maintaining voltage compatibility.
Solution Approach 2:
The I/O interface circuit is segmented into multiple stages: an I/O pad operating at external voltage, an intermediate voltage node, and the pull-up PMOS transistor controlled at internal supply voltage. This segmentation allows each component to operate at its optimal voltage level, preventing leakage while maintaining adaptability.
2Loss of energy
If additional pads or transistors are added to prevent leakage current, then leakage current is reduced, but the circuit complexity increases
Solution Approach 1:
The intermediate voltage node serves multiple functions simultaneously: it prevents leakage current, enables voltage level translation, and provides a control point for the pull-up transistor. This multi-functionality achieves leakage prevention without requiring additional dedicated components, thus avoiding increased circuit complexity.
3Speed
If the I/O pad voltage is allowed to swing freely, then the I/O interface speed is improved, but hot-carrier injection occurs when transitioning from receiving to transmission mode
Solution Approach 1:
Before the I/O pad voltage swings to high levels during transmission mode, the pull-up PMOS transistor is pre-enabled through the intermediate voltage node. This preliminary action ensures that the transistor is already in the correct state to handle the voltage transition, preventing hot-carrier injection while maintaining fast switching performance.
Solution Approach 2:
The intermediate voltage node provides feedback control for the pull-up PMOS transistor based on the I/O pad voltage state. This feedback mechanism ensures the transistor is enabled or disabled at the appropriate times, preventing hot-carrier injection during mode transitions while allowing full voltage swing for high-speed operation.
4Use of energy by moving object
If supply voltage is scaled down to reduce power consumption, then power consumption is reduced, but leakage current and hot-carrier injection problems worsen in mixed-voltage interfaces
Solution Approach 1:
The patent introduces a voltage dimension separation by operating the pull-up PMOS transistor at the internal supply voltage level while allowing the I/O pad to operate at external voltage levels. This dimensional separation enables low-voltage operation for the core circuit (reducing power consumption) while maintaining compatibility with higher voltage external signals through the intermediate voltage node, thus improving reliability without increasing power consumption.
Data Source
AI summary
An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.