Gated Ferroelectric Memory Cells With Vertical Selector Switching
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Solution Overview
Problem
Existing memory technologies face challenges in scaling down while maintaining memory cell density and efficiency, particularly due to size limitations of CMOS transistors, which hinder the development of more compact and densely packed memory devices.
Innovation Solution
The formation of gated ferroelectric memory devices in the Back-End-Of-Line (BEOL) using a vertical field-controlled current selector switch and ferroelectric dielectric layers, allowing for a more compact configuration with improved gate control and higher memory cell density by leveraging smaller area requirements for the field-controlled vertical current switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transistors are used for memory cell selection, then reliable switching function is achieved, but device area increases and memory cell density decreases
Solution Approach 1:
The patent extracts the selection function from conventional CMOS transistors and implements it using a vertical field-controlled current selector switch. This selector switch is formed separately from the memory cell structure itself, allowing the memory cell to be minimized in area while the selection function is performed by the dedicated vertical switch structure.
Solution Approach 2:
The patent transitions from planar CMOS transistor selection to vertical field-controlled current selector switch. The vertical switch extends in the vertical dimension rather than occupying lateral space, enabling memory cells to be packed more densely in the planar direction while selection is achieved through vertical field control.
2Quantity of substance
If memory cell size is reduced to increase density, then memory cell density improves, but gate control capability deteriorates
Solution Approach 1:
The patent moves gate control from the planar dimension to the vertical dimension through the gate dielectric layer and gate electrode. This vertical gate structure provides effective control over the channel current while allowing the memory cell footprint to be minimized, as the control field extends vertically rather than requiring lateral gate width.
Solution Approach 2:
The patent segments the memory device into distinct functional components: the memory cell (with minimal area for storage), the vertical field-controlled current selector switch (for selection), and the gate structure (for control). This segmentation allows each component to be optimized independently, with the gate providing effective control without increasing the memory cell area.
3Ease of manufacture
If conventional memory structures are used, then manufacturing process is simple, but memory cell density and gate control are limited
Solution Approach 1:
The patent forms the vertical field-controlled current selector switch and gate dielectric layer as preliminary structures before completing the memory cell formation. This preliminary action allows the selection and control functions to be established early in the process, enabling subsequent memory cell layers to be deposited and patterned with higher density without complicating the overall manufacturing flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell density and improves gate control, enabling more efficient and compact memory device configurations compared to conventional structures, while maintaining the non-volatility and data storage capabilities of ferroelectric materials.
Implementation Method 1
A ferroelectric material refers to a material that can maintain electrical polarization in the absence of external electrical field. The electrical polarization in a ferroelectric material has a hysteresis effect
Implementation Method 2
The electrical polarization in a ferroelectric material has a hysteresis effect, enabling encoding of a data bit as a polarization direction within the ferroelectric material
Implementation Method 3
In a ferroelectric tunnel junction device, a change in the direction of polarization causes a change in tunneling resistance, which can be employed to measure the direction of the electrical polarization and extract the value of the data bit stored in the ferroelectric tunnel junction
Data Source
AI summary
A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.