Clock Input Buffer Enable Circuit for LPDDR2 Power Saving
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Solution Overview
Problem
Clock input buffers in low power double data rate 2 (LPDDR2) memory circuits consume power even when the clock is stable due to their implementation with differential amplifiers, leading to inefficiencies in power management.
Innovation Solution
An enable circuit is implemented to power down the clock input buffer and quickly enable it in response to clock signal toggles, using a clock detector to sense toggling and control the buffer's enable state, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the clock input buffer is implemented with a differential amplifier to ensure stable clock signal processing, then the clock signal stability is improved, but the power consumption increases even when the clock is stable
Solution Approach 1:
The clock input buffer is transformed from a static always-on component to a dynamic component that can switch between enabled and disabled states. The enable circuit responds to clock signal transitions by dynamically controlling the buffer's operational state, allowing it to be disabled during stable periods and quickly enabled when toggling occurs.
Solution Approach 2:
The buffer operation is converted from continuous to periodic, activated only when clock signal toggling is detected. The enable circuit monitors for transitions and periodically enables the buffer only during necessary periods, rather than maintaining continuous operation during stable clock states.
2Use of energy by moving object
If the clock input buffer is disabled to reduce power consumption, then the power usage is improved, but the response time to restore clock functionality deteriorates
Solution Approach 1:
The enable circuit continuously monitors the clock signal for transitions even when the buffer is disabled. By detecting toggles in advance and preparing the enable signal, the system ensures immediate buffer activation when needed, eliminating startup delays while maintaining power savings during stable periods.
Solution Approach 2:
The enable circuit acts as an intermediary between the clock signal and the buffer, mediating the connection by controlling when the buffer is active. This intermediary continuously watches for transition events and rapidly establishes the buffer connection when toggling is detected, ensuring fast response without continuous buffer operation.
Data Source
AI summary
An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles of the clock signal, the buffer is automatically powered up.