Differential Amplifier Current Feedback for Balanced Edge Delays
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Solution Overview
Problem
In semiconductor integrated circuit devices, the differential amplifier circuit's asymmetric response to rising and falling input signal waveforms leads to pin-to-pin skew, reducing timing margins and affecting data transfer reliability as data transfer rates increase.
Innovation Solution
A differential amplifier circuit with a first differential input section and a second differential input section that detects current and feeds it back to a tail current source to control the tail current, ensuring balanced response times for both rising and falling input signal waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased, then productivity is improved, but timing margin decreases leading to reduced reliability
Solution Approach 1:
The patent applies preliminary action by adjusting the tail current in advance based on the input signal level before the actual data transfer occurs. The tail current is set to a first value when the input signal is at a low level and to a second value (different from the first) when the input signal is at a high level. This preliminary adjustment ensures that the differential amplifier circuit is optimally prepared to handle both rising and falling edges of input signals, thereby maintaining consistent response times and preserving timing margins even at high data transfer rates.
2Speed
If differential amplifier circuit response time is optimized for one edge, then speed is improved, but response time difference between rising and falling edges increases causing pin-to-pin skew
Solution Approach 1:
The patent applies dynamics by making the tail current adjustable and variable rather than fixed. The tail current dynamically changes between a first value and a second value depending on the input signal level. This dynamic adjustment allows the differential amplifier circuit to optimize its response characteristics for both rising and falling edges, ensuring that response times remain consistent across different signal transitions and eliminating pin-to-pin skew.
Solution Approach 2:
The patent applies parameter changes by modifying the tail current parameter based on the input signal level. When the input signal level changes (from low to high or high to low), the tail current parameter is adjusted accordingly. This parameter change approach allows the circuit to maintain balanced response times for both rising and falling edges, resolving the issue of response time inconsistency without compromising speed.
Data Source
AI summary
An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.