Memory I/O Block Resynchronization for DDR Timing Closure
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Solution Overview
Problem
Programmable devices face challenges in implementing high-speed double data rate memory interfaces due to the high demand on programmable logic resources and the introduction of timing constraints, which limits their maximum operating frequency and increases design complexity, especially as memory specifications like DDR2 and DDR3 require faster data rates and more complex clock generation.
Innovation Solution
The implementation of resynchronization registers within I/O blocks of programmable logic devices reduces the need for core registers and provides flexibility for read and write leveling, using half-rate registers to operate at half the frequency of double data rate interfaces, and employing PVT-compensated delay chains for clock generation, allowing for more efficient data transfer and reduced process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If resynchronization registers are implemented in the programmable device core, then double data rate interfaces can be supported, but logic resources are consumed and timing constraints increase
Solution Approach 1:
The patent segments the register functionality by implementing resynchronization registers specifically within the I/O bank rather than in the programmable device core. This separation allows the core to remain simple while the I/O bank handles the complex double data rate synchronization operations independently.
Solution Approach 2:
The I/O bank acts as an intermediary between the external double data rate interface and the programmable device core. The resynchronization registers in the I/O bank convert double data rate signals into single data rate signals, mediating the interface complexity away from the core logic.
2Productivity
If programmable logic operates at double data rate frequency, then data transfer speed increases, but timing closure becomes more difficult
Solution Approach 1:
The patent implements dynamic resynchronization where the I/O bank can adjust its internal timing and phase alignment dynamically to accommodate different double data rate frequencies and timing requirements, allowing timing closure without limiting the data transfer speed.
Solution Approach 2:
The resynchronization registers perform preliminary conversion of double data rate signals to single data rate signals before data enters the programmable device core. This preliminary action simplifies subsequent timing requirements in the core logic.
3Adaptability or versatility
If more core registers are used for double data rate functions, then interface functionality is achieved, but available resources for other design functions are reduced
Solution Approach 1:
The patent extracts the resynchronization register functionality from the programmable device core and places it in the I/O bank. This extraction frees up core logic resources while maintaining the necessary double data rate interface functionality through the I/O bank's dedicated registers.
4Speed
If I/O blocks are optimized for double data rate communications, then operating frequency increases, but flexibility for other interfaces may be reduced
Solution Approach 1:
The I/O bank is designed with universal resynchronization registers that can handle multiple interface types including double data rate, single data rate, and other high-speed interfaces. The same hardware structure adapts to different protocols, maintaining flexibility while optimizing for high-frequency operation.
Data Source
AI summary
I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.