Self-Reset Memory Clock Buffer With Tri-State Keeper Feedback
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Solution Overview
Problem
Conventional clock buffer circuits in memory devices face issues such as reliance on hard delays leading to timing violations, increased circuit area due to multiple transistors, high load on external clock signals, and failure at lower supply voltages due to contention between clock generator and keeper circuit.
Innovation Solution
A self-reset clock buffer design utilizing a cross-coupled logic circuit with feedback loop, reducing the need for hard delays, eliminating one nFET transistor, and replacing the latch with a tri-state inverter to enhance reliability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit is used to ensure the output is pulled down before pull down is disabled, then the clock generator reliability is improved, but the chip select hold time increases and timing violations occur
Solution Approach 1:
The patent implements a feedback mechanism where the clock driver monitors the state of the output clock signal and automatically disables the pull-down path once the output is confirmed to be pulled down. This eliminates the need for a fixed delay circuit while ensuring reliable operation, thereby reducing the chip select hold time requirement without sacrificing reliability.
Solution Approach 2:
The clock driver performs self-checking by monitoring its own output state and automatically controlling the pull-down disable timing. This self-service mechanism eliminates the need for external delay circuits and manual timing adjustment, allowing the system to determine the optimal disable time dynamically based on actual output conditions.
2Ease of manufacture
If two nFET transistors are used in the pull-down circuit to combine clock and delayed clock signals, then the logic function is achieved, but the circuit area increases and storage density decreases
Solution Approach 1:
The patent removes one of the two nFET transistors from the pull-down circuit by extracting only the essential logic function needed. The simplified circuit achieves the required logic operation using a single nFET combined with the feedback mechanism, thereby reducing circuit area while maintaining the necessary logic functionality.
Solution Approach 2:
The patent changes the operational parameters of the remaining nFET by utilizing feedback control to dynamically adjust its switching behavior. This allows the single transistor to perform the logic function that previously required two transistors, achieving area reduction without sacrificing logic capability.
3Ease of manufacture
If two nFET transistors are used in the pull-down circuit, then the logic function is achieved, but the capacitance increases the load on the external clock
Solution Approach 1:
The patent extracts and removes the excess capacitance by eliminating one of the two nFET transistors from the circuit. This reduction in transistor count directly decreases the total capacitance loading the external clock signal, thereby reducing the clock load while maintaining the essential logic function through the simplified circuit design.
4Duration of action of stationary object
If a latch is used in the keeper circuit, then the clock signal is maintained, but contention occurs between clock generator and keeper circuit at low supply voltages
Solution Approach 1:
The patent replaces the latch-based keeper circuit with a feedback-based keeper that monitors the clock signal state and adjusts its maintaining action accordingly. This feedback mechanism prevents contention by ensuring the keeper only acts when necessary and does not conflict with the clock generator, even at low supply voltages where contention previously caused instability.
Solution Approach 2:
The keeper circuit performs self-regulation by monitoring the clock signal state and automatically adjusting its maintaining behavior. This self-service approach eliminates the need for a latch that could cause contention, allowing the keeper to maintain the clock signal reliably without conflicting with the generator across various supply voltage conditions.
Data Source
AI summary
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.